PE33241 Datasheet, PDF (6/13 Pages) Peregrine Semiconductor – UltraCMOS Integer-N PLL Frequency Synthesizer for Low Phase Noise Applications

PE33241
Preliminary Specification
Table 6. AC Characteristics: V_DD = 2.65 to 2.95V, -40°C < T_A < 85°C, unless otherwise specified (continued)
Symbol
Parameter
Condition
Min
Typical
Max
Unit
SSB phase noise 5/6 prescaler (F_in = 3 GHz, F_c = 50 MHz, LBW = 500 kHz)
_N
Phase noise
100 Hz offset
_N
Phase noise
1 kHz offset
_N
Phase noise
10 kHz offset
_N
Phase noise
100 kHz offset
SSB phase noise 10/11 prescaler (F_in = 3 GHz, F_c = 50 MHz, LBW = 500 kHz)
_N
Phase noise
100 Hz offset
_N
Phase noise
1 kHz offset
_N
Phase noise
10 kHz offset
_N
Phase noise
100 kHz offset
Phase noise figure of merit (FOM)
-95
-102
-112
-116
-92
-99
-109
-114
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
FOM_flicker
Flicker figure of merit
5/6 prescaler
10/11 prescaler
-263
-260
dBc/Hz
dBc/Hz
FOM_floor
Floor figure of merit
5/6 prescaler
10/11 prescaler
-230
-228
dBc/Hz
dBc/Hz
FOM_flicker
FOM_floor
FOM_total
PN_flicker = FOM_flicker + 20log (f_vco) - 10log (f_offset)
PN_floor = FOM_floor + 10log (f_pfd) + 20log (f_vco/f_pfd)
PN_total = 10log (10 [PN_flicker/10] + 10 [PN_floor/10])
dBc/Hz
dBc/Hz
dBc/Hz
Notes:
1. Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification
2. CMOS logic levels can be used to drive the reference input. If the VDD of the CMOS driver matches the VDD of the PLL IC, then the reference input can be DC
coupled. Otherwise, the reference input should be AC coupled. For sine-wave inputs, the minimum amplitude needs to be 0.5 Vpp. The maximum level should be
limited to prevent ESD diodes at the pin input from turning on. Diodes will turn on at one forward-bias diode drop above VDD or below GND. The DC voltage at the
Reference input is VDD/2
3. Parameter is guaranteed through characterization only and is not tested
4. Parameters below are not tested for die sales. These parameters are verified during the element evaluation
5. 0 dBm minimum is recommended for improved phase noise performance when sine-wave is applied
6. +2 dBm or higher is recommended for improved phase noise performance
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