PE33241 Datasheet, PDF (2/13 Pages) Peregrine Semiconductor – UltraCMOS Integer-N PLL Frequency Synthesizer for Low Phase Noise Applications

Figure 2. Pin Configurations (Top View)
PE33241
Preliminary Specification
Figure 3. Package Type
48-lead 7x7 mm QFN
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Pin Name
V_DD
R4
R5
A3
N/C
GND
M3
M2
M1
M0
Interface Mode
Both
Direct
Direct
Direct
Both
Both
Direct
Direct
Direct
Direct
Type
Note 1
Input
Input
Input
Note 3
Input
Input
Input
Input
Description
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
R counter bit 4
R counter bit 5
A counter bit 3
No connect
Ground
M counter bit 3
M counter bit 2
M counter bit 1
M counter bit 0
11
V_DD
12
GND
13
M8
14
M7
SCLK
15
M6
SDATA
16
M5
S_WR
17
M4
Both
Both
Direct
Direct
Serial
Direct
Serial
Direct
Serial
Direct
Note 1
Input
Input
Input
Input
Input
Input
Input
Input
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
Ground
M counter bit 8
M counter bit 7
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”)
or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk
M counter bit 6
Binary serial data input. Input data entered MSB first
M counter bit 5
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary
register data is transferred to the secondary register on S_WR or Hop_WR rising edge
M counter bit 4
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Document No. DOC-15014-3 │ UltraCMOS^® RFIC Solutions