PE33241 Datasheet, PDF (3/13 Pages) Peregrine Semiconductor – UltraCMOS Integer-N PLL Frequency Synthesizer for Low Phase Noise Applications

PE33241
Preliminary Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Description
18
GND
19
Direct
20
A0
E_WR
21
A1
22
A2
23
V_DD
24
N/C
25
Pre_en
26
Pre_5/6_Sel
27
V_DD
28
Fi͞ n
29
F_in
30
GND
31
Dout
32
Cext
33
LD
34
V_DD
35
PD_D̅
36
PD_U̅
37
V_DD
38
V_DD
39
f_r
40
V_DD
41
ENH
42
GND
43
N/C
44
R0
45
R1
46
R2
47
R3
48
GND
Both
Direct
Direct
Serial
Direct
Direct
Both
Both
Direct
Direct
Both
Both
Both
Both
Serial
Both
Both
Both
Both
Both
Both
Both
Both
Both
Serial
Both
Both
Direct
Direct
Direct
Direct
Both
Input
Input
Input
Input
Input
Note 1
Note 3
Input
Input
Note 1
Input
Input
Output
Output
Output
Note 1
Output
Output
Note 1
Note 1
Input
Note 1
Input
Note 3
Input
Input
Input
Input
Ground
Select “high” enables Direct Mode. Select “low” enables Serial Mode
A counter bit 0
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk
A counter bit 1
A counter bit 2
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
No connect
Prescaler enable, active “low”. When “high”, F_in bypasses the prescaler
5/6 modulus select, active “high.” When “low,” 10/11 modulus selected
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
Prescaler complementary input. A 22 pF bypass capacitor should be placed as close
as possible to this pin and be connected in series with a 50Ω resistor to ground
Prescaler input from the VCO, 5 GHz max frequency. A 22 pF coupling capacitor
should be placed as close as possible to this pin and be connected in shunt to a
50Ω resistor to ground
Ground
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming
Logical “NAND” of PD_D and PD_U terminated through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”)
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
PD_D is pulse down when f_p leads f_c
PD_U is pulse down when f_c leads f_p
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
Reference frequency input
Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional
Ground
No connect
R counter bit 0
R counter bit 1
R counter bit 2
R counter bit 3
Ground
Notes: 1. VDD pins 1, 11, 23, 27, 34, 37, 38 and 40 are connected by diodes and must be supplied with the same positive voltage level
2. All digital input pins have 70 kΩ pull-down resistors to ground
3. No connect pins can be left open or floating
Document No. DOC-15014-3 │ www.psemi.com
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