PM4332 Datasheet, PDF (86/446 Pages) PMC-Sierra, Inc – HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PRELIMINARY
DATA SHEET
PMC-2011402
ISSUE 1
PM4332 TE-32
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
9.18 Microprocessor Interface
The Microprocessor Interface Block provides normal and test mode registers, the
interrupt logic, and the logic required to connect to the Microprocessor Interface.
The Register Memory Map in Table 2 shows where the normal mode registers
are accessed. The resulting register organization splits into sections: Master
configuration registers, T1/E1 Framer registers and SBI registers.
On power up reset the TE-32 defaults to 32 T1 framers with the SBI buses
disabled. System side access defaults to the SBI bus without any tributaries
enabled which will leave the SBI Drop bus tristated. By default interrupts will not
be enabled and automatic alarm generation is disabled. For proper operation
some register configuration is necessary.
Table 2
- Register Memory Map
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x0010
0x0011
Register
Revision
Global Reset
Global Configuration
SPE #1 Configuration
SPE #2 Configuration
SPE #3 Configuration
Bus Configuration
Global Performance Monitor Update
Reference Clock Select
Recovered Clock#1 Select
Recovered Clock#2 Select
Recovered Clock#3 Select
Master H-MVIP Interface Configuration
Master Clock Monitor #1
Master Interrupt Source
Master Interrupt Source T1E1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
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