PM4332 Datasheet, PDF (137/446 Pages) PMC-Sierra, Inc – HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PRELIMINARY
DATA SHEET
PMC-2011402
ISSUE 1
PM4332 TE-32
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
Register 0x0051: RPCC-MVIP Indirect Channel Address Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
CADDR[6]
CADDR[5]
CADDR[4]
CADDR[3]
CADDR[2]
CADDR[1]
CADDR[0]
Default
X
0
0
0
0
0
0
0
This register provides the channel address number used to access the RPCC-
MVIP context RAM.
CADDR[6:5] is the SPE index and ranges from 1 to 2. CADDR[4:0] is the
tributary index and ranges from 1 to 16.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
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