PM4332 Datasheet, PDF (379/446 Pages) PMC-Sierra, Inc – HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PRELIMINARY
DATA SHEET
PMC-2011402
ISSUE 1
PM4332 TE-32
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
12 OPERATION
12.1 SLC96
The following is a comprehensive discussion of the roles and responsibilities of
TE-32 and external logic in the support of the SLC96 standard, Bellcore
TR-TSY-000008. While the TE-32 handles most of the protocol functions, some
external processing is required, especially of the datalink transported in the Fs
bits.
12.1.1 Transmit
While the TE-32 supports transmission of AIS and the Yellow alarm, and supports
signaling insertion, it is the responsibility of external logic to generate all F-bits.
This means valid Ft and Fs bits as well as the datalink. To pass the F-bits
transparently, the FDIS context bit must be set to logic 1 through the T1/E1
Transmitter Indirect Channel Data registers.
The TE-32 can insert robbed bit signaling. For the TE-32 to insert the signaling
into the correct frames (6^th and 12^th), it must know the multiframe alignment
consistent with the encoding of the F-bits. Therefore, it is imperative a multiframe
indication is provided by the system interface. For the H-MVIP interface, this is
effected by setting the CMMFP bit of the Master H-MVIP Interface Configuration
register and asserting the CMVFPB input every 48 frames. The F-bit is encoded
as per Table 28. For the SBI interface, the PPSSSSFR octets (those following
V5) communicate multiframe alignment, signaling and the F-bits. The
TRIB_TYP[1:0] bits of the EXSBI Tributary Control Indirect Access Data register
should be set to “00” to configure the tributary to “Framed with CAS”.
Because the F-bits are being sourced from the system interface, controlled frame
slips must be avoided, if the TX-ELST is being used, to maintain superframe
integrity. The T1/E1 transmit clock must be referenced to CTCLK. For H-MVIP,
CTCLK must be frequency locked to CMVFPB. For SBI, CTCLK must be
frequency locked to SREFCLK. Two alternate configurations for SBI avoid the
need for the TX-ELST: the transmit clock is slaved to the data rate at the system
interface or the TE-32 acts as a timing master using the AJUST_REQ output to
set the data rate.
Insertion of nine state signaling is straight forward. A sixteen bit encoding (i.e.
ABCD) is used regardless of whether the signaling is inserted from the system
interface or via register access through the T1/E1 Transmit Per-Channel
Controller. The ABCD state is sampled every 24 frames. The “AB” values are
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