PM4332 Datasheet, PDF (405/446 Pages) PMC-Sierra, Inc – HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PRELIMINARY
DATA SHEET
PMC-2011402
ISSUE 1
PM4332 TE-32
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
On the line side, the signaling multiframe alignment is not communicated; the PP
octet is irrelevant. The E1 frame establishes signaling multiframe assuming
TS#16 contains a valid frame alignment pattern.
Table 27 - E1 Channel Associated Signaling bits
TS#16[0:3]
TS#16[4:7]
PP
RRRR
RRRR
00
ABCD1
ABCD16
00
ABCD2
ABCD17
00
ABCD3
ABCD18
00
ABCD4
ABCD19
00
ABCD5
ABCD20
00
ABCD6
ABCD21
00
ABCD7
ABCD22
00
ABCD8
ABCD23
00
ABCD9
ABCD24
00
ABCD10
ABCD25
00
ABCD11
ABCD26
00
ABCD12
ABCD27
00
ABCD13
ABCD28
00
ABCD14
ABCD29
00
ABCD15
ABCD30
C0
E1 tributary asynchronous timing is compensated via the V3 octet. E1 tributary
link rate adjustments are optionally passed across the SBI via the V4 octet. E1
tributary alarm conditions are optionally passed across the SBI bus via the link
rate octet in the V4 location.
In synchronous mode, the E1 tributary mapping is fixed to that shown in Table 26
and rate justifications are not possible using the V3 octet. The clock rate
information within the link rate octet in the V4 location is not used in synchronous
mode.
12.11 H-MVIP Data Format
The H-MVIP data and Channel Associated Signaling interfaces on the TE-32 are
able to carry all the DS0s for the T1s or all timeslots for the E1s. The E1s and
T1s may be mixed on a per SPE basis, so each H-MVIP signal will be carrying
only E1 or T1 data. When carrying timeslots from E1s the H-MVIP frame is
completely filled with 128 timeslots from four E1s but when carrying DS0s from
four T1s there are not enough DS0s to completely fill the 128 byte frame. Table
28 shows how the DS0s and CAS bits of four T1s are formatted in the 128
timeslot H-MVIP frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
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