PM4332 Datasheet, PDF (205/446 Pages) PMC-Sierra, Inc – HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PRELIMINARY
DATA SHEET
PMC-2011402
ISSUE 1
PM4332 TE-32
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
Register 0x0107: TPCC Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
W12C
R/W
R/W
Function
Unused
Unused
Unused
INTE
INBANDCTL
XFERI
XFERE
PCCE
Default
X
X
X
0
0
X
0
0
INTE:
If this bit is a logic 1, the TPRBS bit of the Master Interrupt Source T1E1
register is logic 1 if at least one of the TPCCI[44:29,16:1] bits is a logic 1.
INBANDCTL:
This bit enables the control of the signaling insertion via an inband
mechanism. If INBANDCTL is logic 1, the robbed bit signaling insertion is
controlled by the third and fourth bits in each octet received on CASED[1:21].
If INBANDCTL is logic 0, robbed bit signaling is strictly controlled by the
TPCC SIGC[1:0] context bits.
INBANDCTL only has effect for T1 tributaries and only if the CAS source is H-
MVIP (i.e. SYSOPT[1:0] register bits are 01 or 11).
XFERI:
The XFERI bit indicates that a transfer of accumulated PRBS error data has
occurred. A logic 1 in this bit position indicates that the holding registers have
been updated. This update is initiated by a write to the Global Performance
Monitor Update register that sets the E1T1_PRBS bit to logic 1.
Logic 1 must be written to this bit to clear it to logic 0.
XFERE:
If this bit is a logic 1, the TPRBS bit of the Master Interrupt Source T1E1
register is logic 1 if the XFERI bit is a logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
196