PM4351-1 Datasheet, PDF (385/485 Pages) PMC-Sierra, Inc – COMBINED E1/T1 TRANSCEIVER/FRAMER

STANDARD PRODUCT
DATA SHEET
PMC-1970624
ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 25 - Transmit Backplane at 8.192 Mbit/s (E1 mode)
BTFP
8. 192 MHz BTCLK
(CMS = 0)
BTPCM X
TS 0
X
X
X
TS 1
X
X
X
BTSIG X
X
X
X
X
X ABCD
X
X
X
A 8.192 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits
of the Transmit Backplane Configuration register to 'b11 and the E1/T1B bit of
the Global Configuration register to a logic 1. In Figure 25, BTFP, BTPCM and
BTSIG are configured to be sampled on the rising edge of BTCLK by setting the
FE and DE bits of the Transmit Backplane Configuration register to logic 1.
TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is
sampled.
Figure 26 - Concentration Highway Interface Timing, Example 1
BTC LK
1
2
3
45
6
7
8
9
10 11 12
BTFP
BTPCM
bit 5 TS 31
bit 6 TS 31
bit 7 TS 31
CER = 4
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
CHI timing is configured by setting the BOFF_EN bit of the Transmit Backplane
Bit Offset register to a logic 1. In Figure 26, the DE and FE register bits are set
to logic 0 so that BTPCM, BTSIG and BTFP are sampled on the falling edge of
BTCLK. CMS is set to logic 0 so that the clock rate is equal to the data rate.
BOFF[2:0] is set to 'b000 so that the receive clock edge (CER) is equal to 4 (as
determined by the table in the Transmit Backplane Bit Offset register description
of BOFF[2:0]) and BTPCM is sampled 4 clock edges after BTFP is sampled.
TSOFF is set to 'b0000000 so that there is no time slot offset.
Figure 27 - Concentration Highway Interface Timing, Example 2
B TC LK
1
2
3
45
6
7
8
9
10 11 12
BTFP
BTPCM
bit 5 TS 31
bit 6 TS 31
bit 7 TS 31
CER = 11
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
PROPRIETARY AND CONFIDENTIAL
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