PM4351-1 Datasheet, PDF (180/485 Pages) PMC-Sierra, Inc – COMBINED E1/T1 TRANSCEIVER/FRAMER

STANDARD PRODUCT
DATA SHEET
PMC-1970624
ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 040H: BTIF Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
NXDS0[1]
NXDS0[0]
CMODE
DE
FE
CMS
RATE[1]
RATE[0]
Default
0
0
1
1
1
0
0
0
NXDS0[1:0]:
The NXDS0[1:0] bits determine the mode of operation when BTCLK clock
master mode is selected (CMODE logic 0), as shown in the following table.
Note that these bits are ignored when clock slave mode is selected (CMODE
logic 1).
Table 27 - Transmit Backplane NXDS0 Mode Selection
NXDS0[1]
0
0
1
1
NXDS0[0] Operation
0
Full Frame
1
56 kbit/s NxDS0
0
64 kbit/s NxDS0
1
64 kbit/s NxDS0 with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is
sampled from the backplane.
When in any of the NxDS0 modes, only those time slots with their IDLE_DS0 bit
cleared (logic 0) are sampled from the backplane. The other time slots, with their
IDLE_DS0 bit set (logic 1), do not contain valid data and will be overwritten with
the per-DS0 idle code. The IDLE_DS0 bits are located in the TPSC Indirect
registers. When in T1 mode, the clock is always gapped during the framing bit
position.
PROPRIETARY AND CONFIDENTIAL
156