PM4351-1 Datasheet, PDF (261/485 Pages) PMC-Sierra, Inc – COMBINED E1/T1 TRANSCEIVER/FRAMER

STANDARD PRODUCT
DATA SHEET
PMC-1970624
ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Nx56k_DET and Nx56k_GEN bits in the Pattern Generator/Detector
Positioning/Control register. The PRGD can also be enabled to work on the
entire DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the
Pattern Generator/Detector Positioning/Control register.
DTRKC:
When the DTRKC bit is set to a logic 1, data from the Data Trunk
Conditioning Code Byte contained within the RPSC indirect registers replaces
the BRPCM output data for the duration of that channel.
When the Receive Backplane Configuration register selects a NxDS0 mode,
the DTRKC bit also controls BRCLK generation. If DTRKC is a logic 1,
BRCLK is held low for the duration of the channel.
STRKC:
When the STRKC bit is set to a logic 1, data from the Signaling Trunk
Conditioning Code Byte contained within the RPSC indirect registers replaces
the BRSIG output data for the duration of that channel.
DMW:
When the DMW bit is set to a logic 1, a digital milliwatt pattern replaces the
BRPCM output data for the duration of that channel. The particular digital
milliwatt pattern used, A-law or u-law, is selected by the DMWALAW bit of this
register.
DMWALAW:
When the DMWALAW bit is set to a logic 1, the digital milliwatt pattern
replacing the BRPCM output data for the duration of that channel is the A-law
pattern (see Table 51). When the DMWALAW bit is set to a logic 0, the
digital milliwatt pattern replacing the BRPCM output data for the duration of
that channel is the µ-law pattern (see Table 52).
SIGNINV:
When the SIGNINV bit is set to a logic 1, the most significant bit of the data
output on the BRPCM pin is the inverse of the received data most significant
bit for that channel.
In T1 mode, the RINV[1] of the and SIGNINV bits can be used to invert data
as shown in Table 37:
PROPRIETARY AND CONFIDENTIAL
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