PM8610 Datasheet, PDF (253/338 Pages) PMC-Sierra, Inc – SBI Bus Serializer / STS-12 Time Slot Interchange

SBS Telecom Standard Product Data Sheet
Preliminary
Register 0BCH: TP8E Test Pattern
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
TP[9]
TP[8]
TP[7]
TP[6]
TP[5]
TP[4]
TP[3]
TP[2]
TP[1]
TP[0]
Default
X
X
X
X
X
X
1
0
1
0
1
0
1
0
1
0
This register contains the test pattern to be inserted into the protection transmit serial data stream.
TP[9:0]
The Test Pattern registers (TP[9:0]) contains the test pattern that is used to insert into the
protection transmit serial data stream for jitter test purpose. When the TPINS bit is set high,
the test pattern stored in TP[9:0] is used to replace all the overhead and payload bytes of the
transmit data stream.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
253
Document ID: PMC-2000168, Issue 3