PM8610 Datasheet, PDF (151/338 Pages) PMC-Sierra, Inc – SBI Bus Serializer / STS-12 Time Slot Interchange

SBS Telecom Standard Product Data Sheet
Preliminary
Register 04BH: OMSU Indirect Time Switch Data
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
VALID
Reserved
IN_BYTE[13]
IN_BYTE [12]
IN_BYTE [11]
IN_BYTE [10]
IN_BYTE [9]
IN_BYTE [8]
IN_BYTE [7]
IN_BYTE [6]
IN_BYTE [5]
IN_BYTE [4]
IN_BYTE [3]
IN_BYTE [2]
IN_BYTE [1]
IN_BYTE [0]
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register contains data read from the time switch RAM after an indirect read operation or data
to be inserted into the time switch RAM during an indirect write operation. The value held in the
ram indicates which byte of the input data bus is to be switched to the output.
VALID
The VALID bit reports the presence of valid data from an indirect read. VALID is set to logic
one when indirect read access returns data from the off-line RAM and remains asserted until
the next time Indirect Time Switch Data register is read.
Reserved
The reserved bit should not be modified.
IN_BYTE[13:0]
The IN_BYTE[13:0] bits indicate which byte in the input frame is to be switched to the
output. In DS0 mode, legal values are 000H to 25F7H (0 to 9719). In column mode, legal
values are 000H to 437H (0 to 1079).
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
151
Document ID: PMC-2000168, Issue 3