PM8610 Datasheet, PDF (186/338 Pages) PMC-Sierra, Inc – SBI Bus Serializer / STS-12 Time Slot Interchange

SBS Telecom Standard Product Data Sheet
Preliminary
Register 07Ch: WPP Performance Counters Transfer Trigger
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
TIP
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
This register controls and monitors the reporting of the error counter registers.
A write in this register will trigger the transfer of the error counters to holding registers where
they can be read. The value written in the register is not important. Once the transfer is initiated,
the TIP bit is set high, and when the holding registers contain the value of the error counters, TIP
is set low.
TIP
The Transfer In Progress bit reflects the state of the TIP output signal. When TIP is high, an
error counter transfer has been initiated, but the counters are not transferred in the holding
register yet. When TIP is low, the value of the error counters is available to be read in the
holding registers. This bit can be poll after an error counters transfer request, to determine if
the counters are ready to be read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
186
Document ID: PMC-2000168, Issue 3