PM8610 Datasheet, PDF (118/338 Pages) PMC-Sierra, Inc – SBI Bus Serializer / STS-12 Time Slot Interchange

SBS Telecom Standard Product Data Sheet
Preliminary
Register 012H: SBS Interrupt Enable Register
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ICMPE
OCMPE
OCOLE[4]
OCOLE[3]
OCOLE[2]
OCOLE[1]
RPE
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ICMPE
The ICMPE interrupt enable bit (ICMPE) is an active high interrupt enable. When ICMPE is
set to a logic one, an interrupt will be asserted on the INTB output when the ICMP_INT bit in
the SBS Interrupt Register is set high. When ICMPE is set to a logic zero, The ICMP_INT
bit will not cause an interrupt.
OCMPE
The OCMPE interrupt enable bit (OCMPE) is an active high interrupt enable. When OCMPE
is set to a logic one, an interrupt will be asserted on the INTB output when the OCMP_INT
bit in the SBS Interrupt Register is set high. When OCMPE is set to a logic zero, The
OCMP_INT bit will not cause an interrupt.
OCOLE[4:1]
The outgoing collision detect interrupt enable bits (OCOLE[4:1] are active high interrupt
enables. When OCOLE[x] is set to a logic one, the occurrence of a collision detection on the
associated outgoing bus will cause an interrupt to be asserted on the INTB output. When
OCOLE[x] is set to a logic zero, outgoing collision detection will not cause an interrupt.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
118
Document ID: PMC-2000168, Issue 3