SAB9076H Datasheet, PDF (9/32 Pages) NXP Semiconductors – Picture-In-Picture PIP controller

Philips Semiconductors
Picture-In-Picture (PIP) controller
Preliminary specification
SAB9076H
FUNCTIONAL DESCRIPTION
Pixel rate
The internal chrominance format used is 4 : 1 : 1. It is
expected that the bandwidth of the input signals is limited
to 4.5 MHz for the Y input and 1.125 MHz for the U/V input.
The Y input is sampled with a 1728 × HS (≈27.0 MHz)
clock and is filtered and down sampled to the internal
864 × HS (≈13.5 MHz) pixel rate.
The U and V inputs are multiplexed and sampled with a
432 × HS clock and down sampled to the internal
216 × HS (≈3.375 MHz) pixel rate.
Acquisition area
Synchronisation is achieved via the acquisition H_Sync and
V_sync pins. With the acquisition fine positioning added to a
system constant the starting point of the acquisition can be
controlled.
The acquisition area is 672 pixels/line and 228 lines/field
for NTSC. Both main and sub-channels are equivalent in
handling the data.
Display mode
The internal display pixel rate is 864 × DPH_sync which is
13.5 MHz. This pixel rate is up sampled by interpolation to
1728 × DPH_sync before the DAC stage.
Display area
The display background is an area of 696 pixels and
238 lines. This can be put on/off by the BGON bit
independent of the PIPON bit. This area can be moved by
the display background fine positioning (BGHFP and
BGVFP registers). Its colour is determined by the BGCOL
and BGBRT registers.
Within this area PIPs are defined dependent on the PIP
mode. The PIP sizes are determined by the display
reduction factors as is shown in Table 2.
The display fine positioning determines the location of the
PIPs with respect to the background. Sub-channel and
main channel both have their independent PIP size and
location control, which is shown in Fig.3.
Table 2 PIP sizes
REDUCTION
H/1
H/2
H/3
H/4
V/1
V/2
V/3
V/4
Pixels
672
336
224
168
−
−
−
−
Lines
−
−
−
−
228
114
76
57
1996 Aug 13
9