SAB9076H Datasheet, PDF(19/32 Page) NXP Semiconductors – Picture-In-Picture PIP controller

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SAB9076H Datasheet, PDF (19/32 Pages) NXP Semiconductors – Picture-In-Picture PIP controller

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Philips Semiconductors

Picture-In-Picture (PIP) controller

Preliminary speciï¬cation

SAB9076H

Additional I2C-bus settings

Table 6 Overview of additional I2C-bus sub-addresses

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

DATA BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

PRIO

note 1

MHRPO31 MHRPO30 MHRPO21 MHRPO20

MHRPN31 MHRPN30 MHRPN21 MHRPN20

MHPIC7 MHPIC6 MHPIC5 MHPIC4

MVPIC7 MVPIC6 MVPIC5 MVPIC4

MHDIS07 MHDIS06 MHDIS05 MHDIS04

MHDIS17 MHDIS16 MHDIS15 MHDIS14

MHDIS27 MHDIS26 MHDIS25 MHDIS24

MHDIS37 MHDIS36 MHDIS35 MHDIS34

MVDIS7 MVDIS6 MVDIS5 MVDIS4

SHRPO31 SHRPO30 SHRPO21 SHRPO20

SHRPN31 SHRPN30 SHRPN21 SHRPN20

SHPIC7 SHPIC6 SHPIC5 SHPIC4

SVPIC7 SVPIC6 SVPIC5 SVPIC4

SHDIS07 SHDIS06 SHDIS05 SHDIS04

SHDIS17 SHDIS16 SHDIS15 SHDIS14

SHDIS27 SHDIS26 SHDIS25 SHDIS24

SHDIS37 SHDIS36 SHDIS35 SHDIS34

SVDIS7 SVDIS6 SVDIS5 SVDIS4

MVRPN1

MHRPO11

MHRPN11

MHPIC3

MVPIC3

MHDIS03

MHDIS13

MHDIS23

MHDIS33

MVDIS3

SHRPO11

SHRPN11

SHPIC3

SVPIC3

SHDIS03

SHDIS13

SHDIS23

SHDIS33

SVDIS3

BIT 2

MVRPN0

MHRPO10

MHRPN10

MHPIC2

MVPIC2

MHDIS02

MHDIS12

MHDIS22

MHDIS32

MVDIS2

SHRPO10

SHRPN10

SHPIC2

SVPIC2

SHDIS02

SHDIS12

SHDIS22

SHDIS32

SVDIS2

BIT 1

SVRPN1

MHRPO01

MHRPN01

MHPIC1

MVPIC1

MHDIS01

MHDIS11

MHDIS21

MHDIS31

MVDIS1

SHRPO01

SHRPN01

SHPIC1

SVPIC1

SHDIS01

SHDIS11

SHDIS21

SHDIS31

SVDIS1

BIT 0

SVRPN0

MHRPO00

MHRPN00

MHPIC0

MVPIC0

MHDIS00

MHDIS10

MHDIS20

MHDIS30

MVDIS0

SHRPO00

SHRPN00

SHPIC0

SVPIC0

SHDIS00

SHDIS10

SHDIS20

SHDIS30

SVDIS0

Note

1. The data bits which are not used should be set to zero.

In Manual mode more PIP modes become available with

the help of register 20H to 32H.

An overview of these I2C-bus registers is given in Table 6.

The meaning and relation of the I2C-bus registers is shown

in Fig.8. The background has a fixed size and can be fine

positioned with the BGHFP and BGHFP bits. The shown

PIPs are only for one channel (Main or Sub), the other

channel has the same control and can be displayed at the

same time. The SDHFP and MDHFP bits determine the

most left shown pixel for this channel in 256 steps of

4 pixels. The SDVFP and MDVFP bits determine the most

upper shown line for this channel in 256 steps of 1 line.

The SHPIC and MHPIC bits determine the horizontal

picture size in 256 steps of 4 pixels, the minimum value is

4 pixels. The SVPIC and MVPIC bits determine the vertical

picture size in 256 steps of 1 line, the minimum value is

1 line. The PIP mode is built-up of a maximum of four

horizontal rows. The minimum is one row, more rows can

be displayed by setting the Vertical Repetition Rate

Number VRPN bits. The distance between the rows can be

set by SVDIS and MVDIS bits. Every row is built-up of a

maximum of four PIPs. The minimum is one PIP and the

distance between the starting points of those PIPs on a

row is determined by SHDIS and MHDIS bits.

SA 20H CONTROL REGISTER

The PRIO bit sets the priority between Main and Sub

channel. If PRIO is set to logic 0, priority is given to the Sub

channel which means that the Sub channel PIPs, if

present, are placed on top of the Main PIPs. If PRIO is set

to logic 1, the Main PIPs are set on top of the Sub PIPs.

The MVRPN and SVRPN bits determine the number of

repeated PIP rows. There is always one row visible of each

channel. If no PIPs should be visible the PIP channel must

be switched off (SA 00, bit 7 or bit 6).

1996 Aug 13

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