SAB9076H Datasheet, PDF (20/32 Pages) NXP Semiconductors – Picture-In-Picture PIP controller

Philips Semiconductors
Picture-In-Picture (PIP) controller
Preliminary specification
SAB9076H
SA 21H AND SA 2AH HORIZONTAL REPETITION OFFSET
REGISTERS FOR ROW 0 TO 3
The horizontal repetition offsets (MHRPO and SHRPO
bits) are strongly related to the horizontal distance (MHDIS
and SHDIS bits). These registers set for each row a certain
grid of possible starting points for the PIPS in that row.
Every grid point has a number 0 (the most left PIP), 1, 2 or
3. The MHRPO and SHRPO bits determine the first PIP
number which will be displayed. This mechanism can be
set for each row.
SA 22H AND SA 2BH HORIZONTAL REPETITION NUMBER
REGISTERS FOR ROW 0 TO 3
The horizontal repetition numbers (MHRPN and SHRPN
bits) determine how many times the PIPs are repeated in
a row, once the first PIP is displayed. The repeated PIPs
stay in the grid determined by the MHDIS and SHDIS bits
for that row. This mechanism can be set for each row
independent.
SA 23H AND SA 24H; SA 2CH AND SA 2DH PICTURE SIZE
REGISTERS
The MHPIC and SHPIC bits determine the horizontal PIP
size in 256 steps of 4 pixels. The MVPIC and SVPIC bits
determine the vertical PIP size in 256 steps of 1 line.
SA 25H AND SA 29H; SA 2EH AND SA 32H PICTURE
DISTANCE REGISTERS
For each row the distance between starting points of PIPs
can be set with the bits MHDIS and SHDIS in 256 steps of
4 pixels. The distance between two rows can be set with
the MVDIS and SVDIS bits in 256 steps of 1 line.
Acquisition Channel ADCs
Both channels convert the analog input signals to digital
signals by means of two ADCs for each channel. The input
levels of the ADCs of each channel are equal and can be
set by the AV_refT and AV_refB pins.
The reference levels are made internally by a resistor
network which divides the analog supply voltage to a
default set of preferred levels. External capacitors are
needed to filter AC components on the reference levels.
The resolution of the ADCs is 8 bit. Differential
Non-Linearity (DNL) is 7-bit; Integral Non-Linearity (INL) is
6-bit, and the sampling is carried out at the system
frequency of 27 MHz for the Y input. The U/V inputs are
multiplexed and sampled at 13.5 MHz. The analog input
signals are amplified to make maximum use of the
dynamic range of the ADCs. A bias voltage V_bias is used
for decoupling AC components on internal references. The
inputs should be AC-coupled and an internal clamping
circuit will clamp the input to AV_refB for the luminance
channels and to ^A-----V----r--^e---^f-^T-----2^–----A----V-----^r-^e---^f--^B-- + ^{L----S-2----B--} for the
chrominance channels. The clamping starts at the active
edge of the burst key.
Output DACs
The digitally processed signals are converted to analog
signals by three 8-bit DACs. The output voltages of these
DACs are default set by the DAV_refT pin for the top level
and DAV_refB pin for the bottom level. Default values are
1.5 V.
External Memory
For the external memory two VDRAMs of type Mitsubishi
M5M442256 are used. They have a storage capacity of
262 144 words of 4-bit each and will be used in parallel.
It is also possible to use a 2 Mbit VDRAM with a storage
capacity of 262 144 words of 8 bit each. An overview of the
timing diagrams is given in Fig.9.
1996 Aug 13
20