SAB9076H Datasheet, PDF (16/32 Pages) NXP Semiconductors – Picture-In-Picture PIP controller

Philips Semiconductors
Picture-In-Picture (PIP) controller
Preliminary specification
SAB9076H
SA 00H PIP REGISTER
The MPIPON and SPIPON bits switch respectively the
main and sub PIPs of the SAB9076H on or off.
The MFREEZE and SFREEZE bits make the current live
pictures for the channels main and sub frozen. The writing
to the VDRAM is stopped. The PIPMODE3 to PIPMODE0
bits set the PIP mode in accordance with Table 3.
The YTH3 to YTH0 bits control the video output. If the
current Y-value is less then YTH × 16 then the fast blank
is switched off, the original live background will be visible.
This feature can be used to pick up sub-titles and display
them as On-Screen Display (OSD) anywhere on the
screen.
SA 03H DISPLAY BACKGROUND FINE POSITIONING REGISTER
SA 01H DISPLAY REGISTER
The M1FLD and S1FLD⁽¹⁾ bits control the use of the
reserved second field in the VDRAM. If this bit is set to
logic 0 then address spaces are reserved for both fields in
the VDRAM. This avoids joint line errors. Whether these
address spaces are used is dependent on the interlacing
of the input signals and the three NONINT bits. If a 1FLD
bit is set to logic 1 then only 1 address space is used in the
VDRAM for both fields. In some PIP modes the use of a
second field is not possible since there is not enough
space in the VDRAM, in these modes the 1FLD bit must be
set to logic 1. DNONINT controls the interlace mode of the
display part. If set to logic 1 then data is only read from one
field in the VDRAM. If set to logic 0 then both fields (if
available) are used for display.
The MNONINT and SNONINT bits control the interlace
mode of the acquisition blocks. If set to logic 1 then data is
only written to one field in the VDRAM (two fields remain
allocated). If set to logic 0 then both fields (if available) are
used for acquisition.
SA 02H DISPLAY REGISTER
The DFILT bit controls an interpolating filter that changes
the internal 864 pixels data rate to the output data rate of
2 × 864 pixels. If DFILT is set to logic 1 then the filter is on.
The BGHFP3 to BGHFP0 bits control the horizontal
display positioning of the background. The resolution is
16 steps of 4 pixels. The BGVFP3 to BGVFP0 bits control
the vertical display positioning of the background.
The resolution is 16 steps of 2 lines/field. The background
fine positioning moves the complete display. It is a general
offset of all the PIP pictures and background. It is intended
only to adjust once the centring of all PIP modes (see
Fig.3).
SA 04H AND SA 05H DISPLAY SUB-CHANNEL FINE
POSITIONING REGISTERS
These registers control the horizontal and vertical fine
positioning of the display sub-channel with respect to the
display background. This is the actual fine positioning (see
Fig.3). The horizontal resolution is 256 steps of 4 pixels
and the vertical resolution is 256 steps of 1 line/field.
SA 06H AND SA 07H DISPLAY MAIN-CHANNEL FINE
POSITIONING REGISTERS
These registers control the horizontal and vertical fine
positioning off the display main-channel with respect to the
display background. This is the actual fine positioning (see
Fig.3). The horizontal resolution is 256 steps of 4 pixels
and the vertical resolution is 256 steps of 1 line/field.
The FILLOFF bit controls filling of PIPs when the PIP mode
is switched. If FILLOFF is set to logic 0 then all PIPs are
filled with a 30% gray until their channel has been updated.
If FILLOFF is set to logic 1 then the VDRAM content is
always visible. This is useful when a new, ‘similar’ to the
previous one, PIP mode is set. The previous data can then
be displayed.
The SMART6 and SKIP6 bits control the data transfer
mode to the external VDRAM. For modes which display a
complete line (672 pixels) a type of data reduction has to
be carried out.
Two transfer modes are available. One is simply skipping
the 8-bit data path to 6-bit (SKIP6). The other is carry out
an intelligent data reduction which retains an 8-bit
resolution (SMART6).
(1) The 1 FLD bits only operate when the NONINT bits of the
corresponding channel is set.
SA 08H DISPLAY REDUCTION FACTORS REGISTER
This register sets the display reduction factors,
independent of the acquisition reduction factors. It sets the
PIP size to a certain default value in such a way that the
border drawn around the PIP is just fitting.
SA 09H ACQUISITION REDUCTION FACTORS REGISTER
This register sets the acquisition reduction factors,
independent of the display reduction factors. If the HRED
is 1 : 1 then the VRED must also be 1 : 1.
Restrictions are:
• The DREDH and AREDH must be the same
• The DREDV is equal or smaller than the AREDV
(e.g DREDV is 1 : 2 and AREDV is 1 : 1).
1996 Aug 13
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