PR31700 Datasheet, PDF (9/36 Pages) NXP Semiconductors – 32-bit RISC microprocessor

Philips Semiconductors
32-bit RISC microprocessor
Preliminary specification
PR31700
NAME
I/O
Bus Arbitration Pins
DREQ*
I
DGRNT*
O
*Active-low signal
NAME
I/O
Clock Pins
SYSCLKIN
I
SYSCLKOUT
O
C32KIN
I
C32KOUT
O
BC32K
O
FUNCTIONS
This pin is used to request external arbitration. If the TESTSIU signal is high and the TESTSIU function has
been enabled, then once /DGRNT* is asserted, external logic can initiate reads or writes to PR31700
processor registers by driving the appropriate input signals. If the TESTSIU signal is low or the TESTSIU
function has not been enabled, then PR31700 memory transactions are halted and certain memory signals
will be tri-stated when /DGRNT* is asserted in order to allow an external master to access memory.
This pin is asserted in response to /DREQ* to inform the external test logic or bus master that it can now
begin to drive signals.
FUNCTIONS
This pin should be connected along with SYSCLKOUT to an external crystal which is the main PR31700
clock source.
This pin should be connected along with SYSCLKIN to an external crystal which is the main PR31700 clock
source.
This pin along with C32KOUT should be connected to a 32.768 KHz crystal.
This pin along with C32KIN should be connected to a 32.768 KHz crystal.
This pin is a buffered output of the 32.768 KHz clock.
NAME
CHI Pins
CHIFS
CHICLK
CHIDOUT
CHIDIN
I/O
FUNCTIONS
I/O
This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes. As an
output, this pin allows PR31700 to be the master CHI sync source. As an input, this pin allows an external
peripheral to be the master CHI sync source and the PR31700 CHI module will slave to this external sync.
I/O
This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output, this pin
allows PR31700 to be the master CHI clock source. As an input, this pin allows an external peripheral to be
the master CHI clock source and the PR31700 CHI module will slave to this external clock.
O
This pin is the CHI serial data output signal.
I
This pin is the CHI serial data input signal.
NAME
IO Pins
IO(6:0)
MIO(1:0)
I/O
FUNCTIONS
I/O
These pins are general purpose input/output ports. Each port can be independently programmed as an
input or output port. Each port can generate a separate positive and negative edge interrupt. Each port
can also be independently programmed to use a 16 to 24 msec debouncer.
I/O
These pins are multi-function input/output ports. Each port can be independently programmed as an input
or output port, or can be programmed for multi-function use to support test signals (for debugging purposes
only). Each port can generate a separate positive and negative edge interrupt. Note that 30 other
multi-function pins are available for usage as multi-function input/output ports. These pins are named after
their respective standard/normal function and are not listed here.
NAME
Reset Pins
/CPURES*
/PON*
I/O
FUNCTIONS
I
This pin is used to reset the CPU core. This pin should be connected to a switch for initiating a reset in the
event that a software problem might hang the CPU core. The pin should also be pulled up to VSTANDBY*
through an external pull-up resistor.
I
This pin serves as the Power On Reset signal for PR31700. This signal must remain low when VSTANDBY
is asserted until VSTANDBY[ is stable. Once VSTANDBY is asserted, this signal should never go low
unless all power is lost in the system.
[VSTANDBY—This signal provides power for the PR31700 and other components in the system that must never lose power. This signal should
always be asserted if there is eithr a good Main Backup Battery, or if a Battery Charger is plugged in.
1998 May 13
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