PR31700 Datasheet, PDF (8/36 Pages) NXP Semiconductors – 32-bit RISC microprocessor

Philips Semiconductors
32-bit RISC microprocessor
Preliminary specification
PR31700
PIN FUNCTIONS
NAME
I/O
Memory Pins
D(31:0)
I/O
A(12:0)
O
ALE
O
RD^*
O
WE*
O
CAS0^* (/WE0)^*
O
CAS^* (/WE1)^*
O
CAS2^* (/WE2)^*
O
CAS3^* (/WE3)^*
O
RAS0^*
O
RAS1^* (/DCS1)^*
O
DCS0^*
O
DCKE
O
DCLKIN
I
DCLKOUT
O
DQMH
O
DQML
O
CS3–0^*
O
MCS3–0^*
O
CARD2CSH^*,L^*
O
/CARD1CSH^*,L^*
O
CARDREG^*
O
CARDIORD^*
O
CARDIOWR^*
O
CARDDIR^*
O
CARD2WAIT^*
I
CARD1WAIT^*
I
*Active-low signal
FUNCTIONS
These pins are the data bus for the system. 8-bit SDRAMs should be connected to bits 7:0 and 16-bit
SDRAMs and DRAMs should be connected to bits 15:0. All other 16-bit ports should be connected to bits
31:16. Of course, 32-bit ports should be connected to bits 31:0. These pins are normally outputs and only
become inputs during reads, thus no resistors are required since the bus will only float for a short period of
time during bus turn-around.
These pins are the address bus for the system. The address lines are multiplexed and can be connected
directly to SDRAM and DRAM devices. To generate the full 26-bit address for static devices, an external
latch must be used to latch the signals using the ALE signal. For static devices, address bits 25:13 are
provided by the external latch and address bits 12:0 (directly connected from PR31700’s address bus) are
held afterward by PR31700 processor for the remainder of the address bus cycle.
This pin is used as the address latch enable to latch A(12:0) using an external latch, for generating the
upper address bits 25:13.
This pin is used as the read signal for static devices. This signal is asserted for reads from /MCS3*-0*,
/CS3*-0*, /CARD2CS* and /CARD1CS* for memory and attribute space, and for reads from PR31700
processor accesses if SHOWPOSEIDON is enabled (for debugging purposes).
This pin is used as the write signal for the system. This signal is asserted for writes to /MCS3*-0*, /CS3*-0*,
/CARD2CS* and /CARD1CS* for memory and attribute space, and for writes to DRAM and SDRAM.
This pin is used as the CAS signal for SDRAMs, the CAS signal for D(7:0) for DRAMs, and the write enable
signal for D(7:0) for static devices.
This pin is used as the CAS signal for D(15:8) for DRAMs and the write enable signal for D(15:8) for static
devices.
This pin is used as the CAS signal for D(23:16) for DRAMs and the write enable signal for D(23:16) for
static devices.
This pin is used as the CAS signal for D(31:24) for DRAMs and the write enable signal for D(31:24) for
static devices.
This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs.
This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1 DRAMs.
This pin is used as the chip select signal for Bank0 SDRAMs.
This pin is used as the clock enable for SDRAMs.
This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data input when
reading from SDRAM and DRAM devices.
This pin is the (nominal) 73.728 MHz clock for the SDRAMs.
This pin is the upper data mask for a 16-bit SDRAM configuration.
This pin is the lower data mask for a 16-bit SDRAM or 8-bit SDRAM configuration.
These pins are the Chip Select 3 through 0 signals. They can be configured to support either 32-bit or 16-bit
ports.
These pins are the Memory Card Chip Select 3 through 0 signals. They only support 16-bit ports.
These pins are the Chip Select signals for PCMCIA card slot 2.
These pins are the Chip Select signals for PCMCIA card slot 1.
This pin is the /REG* signal for the PCMCIA cards.
This pin is the /IORD* signal for the PCMCIA IO cards.
This pin is the /IOWR* signal for the PCMCIA IO cards.
This pin is used to provide the direction control for bi-directional data buffers used for the PCMCIA slot(s).
This signal will assert whenever /CARD2CSH* or /CARD2CSL* or /CARD1CSH* or /CARD1CSL* is
asserted and a read transaction is taking place.
This pin is the card wait signal from PCMCIA card slot 2.
This pin is the card wait signal from PCMCIA card slot 1.
1998 May 13
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