74F821 Datasheet, PDF (9/18 Pages) NXP Semiconductors – Bus interface registers

Philips Semiconductors
Bus interface registers
Product specification
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F826
14
CE
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
10
13
CP
V_CC = Pin 24
GND = Pin 12
MR ¹¹
1
OE0
OE1 ²
23
OE2
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
22
21
20
19
18
17
16
15
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SF00505A
FUNCTION TABLE FOR 74F825 AND 74F826
INPUTS
OUTPUTS
74F825
74F826
OPERATING MODE
OEn
MR
CE*
CP
Dn
Q
Q
L
L
X
X
X
L
L
Clear
L
H
L
↑
h
H
L
H
L
↑
l
L
L
Load and read data
H
L
H
H
X
X
NC
NC
Hold
H
X
X
X
X
Z
Z
High impedance
H=
h=
L=
l=
NC=
X=
Z=
*=
↑=
High-voltage level
High state must be present one setup time before the low-to-high clock transition
Low-voltage level
Low state must be present one setup time before the low-to-high clock transition
No change
Don’t care
High impedance “off” state
Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders
or other potentially glitch prone device on the CE input.
Low-to-high clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
V_CC
V_IN
I_IN
V_OUT
I_OUT
T_amb
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free-air temperature range
Commercial range
Industrial range
T_stg
Storage temperature range
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V_CC
128
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
°C
1996 Jan 05
9