74F821 Datasheet, PDF (3/18 Pages) NXP Semiconductors – Bus interface registers

Philips Semiconductors
Bus interface registers
Product specification
74F821/822/823/824/825/826
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
Dn
Data inputs
74F821
CP
Clock input
74F822
OE
Output enable input (active low)
Qn, Qn Data outputs
Dn
Data inputs
CP
Clock input
74F823
CE
Clock enable input (active low)
74F824
MR
Master reset input (active low)
OE
Output enable input (active low)
Qn, Qn Data outputs
Dn
Data inputs
CP
Clock input
74F825
CE
Clock enable input (active low)
74F826
MR
Master reset input (active low)
OE
Output enable input (active low)
Qn, Qn Data outputs
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/3.0
1200/106.7
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
1.0/3.0
1200/106.7
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
1.0/3.0
1200/106.7
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
24mA/64mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
20µA/1.8mA
24mA/64mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
20µA/1.8mA
24mA/64mA
PIN CONFIGURATION – 74F821
LOGIC SYMBOL – 74F821
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
GND 12
24 V_CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
2 3 4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13
CP
1
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
V_CC = Pin 24
GND = Pin 12
23 22 21 20 19 18 17 16 15 14
SF00483
SF00482
1996 Jan 05
3