74F821 Datasheet, PDF (8/18 Pages) NXP Semiconductors – Bus interface registers

Philips Semiconductors
Bus interface registers
Product specification
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F824
14
CE
D0
D1
D2
D3
D4
D5
D6
D7
D8
2
3
4
5
6
7
8
9
10
13
CP
MR ¹¹
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
1
OE
V_CC = Pin 24
GND = Pin 12
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
SF00503A
FUNCTION TABLE for 74F823 and 74F824
INPUTS
OUTPUTS
74F823
74F824
OPERATING MODE
OE
MR
CE*
CP
Dn
Q
Q
L
L
X
X
X
L
L
Clear
L
H
L
↑
h
H
L
H
L
↑
l
L
L
Load and read data
H
L
H
H
X
X
NC
NC
Hold
H
X
X
X
X
Z
Z
High impedance
H=
h=
L=
l=
NC=
X=
Z=
*=
↑=
High-voltage level
High state must be present one setup time before the low-to-high clock transition
Low-voltage level
Low state must be present one setup time before the low-to-high clock transition
No change
Don’t care
High impedance “off” state
Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders
or other potentially glitch prone device on the CE input.
Low-to-high clock transition
LOGIC DIAGRAM FOR 74F825
14
CE
CP ¹³
V_CC = Pin 24
GND = Pin 12
MR ¹¹
1
OE0
2
OE1
OE2 ²³
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
10
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
D ^CP
RQ
22
Q0
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
SF00504A
1996 Jan 05
8