XA-H3 Datasheet, PDF (7/36 Pages) NXP Semiconductors – CMOS 16-bit highly integrated microcontroller

Philips Semiconductors
CMOS 16-bit highly integrated microcontroller
Preliminary specification
XA-H3
PIN DESCRIPTIONS
Mnemonic
V_SS
Lqfp
Pin No.
1, 19, 28,
44, 59,
76, 88
Type
I
Ground: 0 V reference.
Name and Function
V_DD
2, 20, 29,
Power Supply: This is the power supply voltage for normal, idle, and power down operation.
43, 62,
I
77, 89
ResetIn
55
Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on
I their default states, and the processor to begin execution at the address contained in the reset
vector.
WAIT/
Size16
52
I
Wait/Size16: During Reset, this input determines bus size for boot device (“1” = 16-bit boot device;
“0” = 8-bit.) During normal operation this is the Wait input (“1” = Wait; “0” = Proceed.)
XTALIn
60
I
Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock
generator circuits.
XTALOut
61
I Crystal 2: Output from the oscillator amplifier.
Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or
CS0
49
O
Flash.) From reset, it is enabled and mapped to an address range based at 000000h. It can be
remapped by software to a higher base in the address map (see the “Memory Interface” chapter in
the XA-H3 User Manual.)
CS1
48
O Chip Select 1*: Chip Selects 1 through 5 come out of reset disabled. They function as normal chip
selects on the H3. CS1 can be “swapped” with CS0 (see the SWAP operation in the “Memory
Controller” chapter of the XA-H3 User Manual.) CS1 is usually mapped to be based at 000000h
after the swap, but is capable of being based anywhere in the 16 MB address space.
CS2
47
O Chip Select 2 *: Active low Chip Selects CS1 through CS5 come out of reset disabled. They can
be programmed to function as normal chip selects. CS2 through CS5 are not used with the
“SWAP” operation (only /CS0 and CS1 can be swapped; see “Memory Controller” chapter in the
XA-H3 User Manual.) They are mappable to any region of the 16 MB address space.
CS3
46
O Chip Select 3 *: See Chip Select 2 for description.
See Pins 56, 57 for 2 additional Chip Selects
WE
50
O Write Enable: Goes active low during all bus write cycles only.
OE
51
O Output Enable: Goes active low during all bus read cycles only.
BLE
54
O Byte Low Enable: Goes active low during all bus cycles that access data bus lines D7 – D0, read
or write.
BHE
53
O Byte High Enable: Goes active low during all bus cycles that access data bus lines D15 – D8,
read or write. Never goes active on an 8-bit bus; always goes active on Reads or Fetches on a
16-bit bus, even if the processor does not need these bits. In other words, all Reads (byte or word)
on a 16-bit bus, assert BHE.
ClkOut
45
O Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may
be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock
output may be disabled by software. WARNING: The capacitive loading on this output must not
exceed 40 pf.
A19 – A0 24 – 21,
18 – 3
O Address[19:0]: These address lines output A19 – A0 during all external bus cycles.
D15 – D0 42 – 30,
27 – 25
I/O Data[15:0]: Bi-directional data bus, D15 – D0; for those bus cycles that are programmed to occur
on an “8-bit bus”, D15 – D8 are unused.
P0.0
90
I/O P0.0_BRG0*: Port 0 Bit 0, or UART0 BRG output, or UART0 TxClk output
P0.1
91
I/O P0.1_RTS0: Port 0 Bit 1 , or UART0 RTS (Request To Send) output.
P0.2
92
I/O P0.2_CTS0: Port 0 Bit 2, or UART0 CTS (Clear To Send) input.
P0.3
93
I/O P0.3_CD0: Port 0 Bit 3, or UART0 Carrier Detect input.
P0.4
94
I/O P0.4_TRClk0: Port 0 Bit 4, or UART0 TR clock input.
P0.5
95
I/O P0.5_RTClk0: Port 0 Bit 5, or UART0 RT clock input.
P0.6
99
I/O P0.6: Port 0 Bit 6
P0.7
100
I/O P0.7: Port 0 Bit 7
TxD0
96
O TxD0: Transmit data for UART0.
See
Note
1
1
1
1
1, 2
1, 2
1
1
1999 Sep 24
7