XA-H3 Datasheet, PDF (22/36 Pages) NXP Semiconductors – CMOS 16-bit highly integrated microcontroller

Philips Semiconductors
CMOS 16-bit highly integrated microcontroller
Preliminary specification
XA-H3
Table 6. Rx DMA modes summary
Mode
Byte Count Source
Maskable Interrupt
Description
Periodic Interrupt
Asynchronous
with Character
Time Out
Loaded by processor into DMA, used by
DMA only to determine the number of
bytes between interrupts. Processor can
calculate the byte count from the DMA
address pointer.
Byte Count can be calculated by software
from the DMA address pointer.
When Byte Counter reaches
zero and is reloaded by DMA
hardware from the byte count
register.
If no character is received
within a specified time out
period, then interrupt.
The DMA channel runs until commanded to
stop by the processor. It generates a
maskable interrupt once per n bytes, where n
is the number written once into the byte count
register by the processor, thus an interrupt is
generated once every n received bytes.
Processor specifies time out period between
incoming characters. If no character is
received within that time, a maskable
interrupt is generated.
Asynchronous
Byte Count can be calculated by software No interrupt generated
without interrupt from the DMA address pointer.
Whenever a new character is received, it is
moved into the memory buffer – no interrupt
is generated.
Data FIFO 3
Data FIFO 1
Data FIFO 2
Data FIFO 0
DMA Control
Segment
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
Rx Time Out
Rx Channel
Data FIFO 3
Data FIFO 1
Data FIFO 2
Data FIFO 0
DMA Control
Segment
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
Figure 5. Rx and Tx DMA Registers
Tx Channel
SU01240
DMA Registers
In addition to the 16-bit Global DMA Interrupt Register (which is shared
by all eight DMA channels), each DMA channel has seven control
registers and a four-byte Data FIFO. The four Rx DMA channels have
one additional register, the Rx Character Time Out Register. All DMA
registers can be read and written in Memory Mapped Register (MMR)
space. These registers are summarized below.
• Global DMA Interrupt Register (not shown in figure): All DMA
interrupt flags are in this register .
• DMA Control Register: Contains the master mode select and
interrupt enable bits for the channel.
1999 Sep 24
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