XA-H3 Datasheet, PDF (21/36 Pages) NXP Semiconductors – CMOS 16-bit highly integrated microcontroller

Philips Semiconductors
CMOS 16-bit highly integrated microcontroller
Preliminary specification
XA-H3
Table 4. Memory interface control registers
Register Name
MRBH “MMR Base Address” High
Reg
Type
SFR
8 bits
Description
This SFR is used to relocate the MMRs. It contains address bits a23 – a16 of the
base address for the 4 kB Memory Mapped Register space. See the User Manual for
using this SFR to relocate the MMRs.
MRBL “MMR Base Address” Low
MICFG MIF Configuration
MBCL Memory Bank Configuration Lock
BiCFG Bank i Configuration
BiAM Bank i Base Address
BiTMG Bank i Timing
SFR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
Contains address bits a15 – a12 of the base address for the 4 kB Memory Mapped
Register space.
Contains the CLKOUT Enable bit.
Contains the bits for locking and unlocking the BiCFG Registers.
Contains the size, type, bus width, and enable bits for Memory Bank i.
Contains the base address bits for Memory Bank i.
Contains the timing control bits for Memory Bank i.
EIGHT CHANNEL DMA CONTROLLER
The XA-H3/H4 has eight DMA channels; one Rx DMA channel
dedicated to each UART Receive (Rx) channel, and one Tx DMA
channel dedicated to each UART Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
Transmit DMA Channel Modes
The four Tx channels have three DMA modes specifically designed
for various applications of the attached UARTs. These modes are
summarized in the following table. Full details for all DMA functions
can be found in the DMA chapter of the XA-H3 User Manual.
Table 5. Tx DMA modes summary
Mode
Tx
Chaining
Byte Count Source
Header in memory
Stop on TC Processor loads Byte Count Register
Periodic
Interrupt
Loaded by processor into DMA, used by
DMA only to determine the number of
bytes between interrupts. Processor can
calculate the byte count from the DMA
address pointer.
Maskable Interrupt
On stop
Byte count completed
(Tx DMA stops)
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte
count register.
Description
DMA channel picks up header from memory at end of
transmission. If byte count in header is greater than zero,
then DMA transmits the number of bytes specified in the
byte count. If byte count equals 0, then a maskable
interrupt is generated. This process repeats until byte count
in data header is zero. See XA-H3 User Manual for details.
Processor loads byte count into DMA. DMA sends that
number of bytes, generates maskable interrupt, and stops.
DMA runs until commanded to stop by processor. CPU
loaded value in Byte Count Register is used to generate
an interrupt for every n bytes. Every time byte counter
rolls over, a new maskable interrupt is generated.
Receive DMA Channel Modes
The Rx DMA channels have two DMA modes specifically designed
for various applications of the attached UARTs. These modes are
summarized in the following table. For full details on implementation
and use, see the XA-H3 User Manual.
1999 Sep 24
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