XA-H3 Datasheet, PDF (29/36 Pages) NXP Semiconductors – CMOS 16-bit highly integrated microcontroller

Philips Semiconductors
CMOS 16-bit highly integrated microcontroller
Preliminary specification
XA-H3
AC ELECTRICAL CHARACTERISTICS (3.3 V +/–10%)
Vdd = 3.3 V +/– 10%; T_amb = –40°C to +85°C ( industrial )
Symbol
Figure
Parameter
Limits
Unit
Min
Max
All Cycles
F_C
t_C
t_CHCX
t_CLCX
t_CLCH
t_CHCL
t_AVSL
t_CHAH
t_CHAV
t_CHSH
t_CHSL
t_CODH
System Clock (internally called CClk) Frequency
13
System Clock Period = 1/FC
13
XTALIN High Time
13
XTALIN Low Time
13
XTALIN Rise Time
13
XTALIN Fall Time
All
Address Valid to Strobe low
All
Address hold after CLKOUT rising edge ⁷
All
Delay from CLKOUT rising edge to address valid
All
Delay from CLKOUT rising edge to Strobe High ⁷
All
Delay from CLKOUT rising edge to Strobe Low ⁷
14
ClkOut Duty Cycle High (into 40 pF max.)
Data Read Only
0
33.33
t_C* 0.5
t_C* 0.4
–
–
t_C – 21
1
–
1
1
t_CHCX–7
30
–
–
–
5
5
–
–
30
28
25
t_CHCX+3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_AHDR
10
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at end
t_C – 12
–
ns
of Data Read Cycle (not code fetch)
Data Read and Instruction Fetch Cycles
t_DIS
t_DIH
t_OHDE
7, 8, 10, 11
7, 8, 10, 11
10
Data In Valid setup to ClkOut rising edge
Data In Valid hold after ClkOut rising edge ²
OE high to XA Data Bus Driver Enable
Write Cycles
32
–
ns
0
–
ns
t_C – 19
–
ns
t_CHDV
t_DVSL
t_SHAH
t_SHDH
9
12
9, 12
9, 12
Clock High to Data Valid
Data Valid prior to Strobe Low
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
Wait Input
–
30
ns
t_C – 23
–
ns
t_C – 25
–
ns
t_C – 25
–
ns
t_WS
15
WAIT setup (stable high or low)prior to CLKOUT rising edge
25
–
ns
t_WH
15
WAIT hold (stable high or low) after CLKOUT rising edge
0
–
ns
NOTE:
1. On a 16-bit bus, if only one byte is being written, then only one of BLE or BHE will go active. On an 8-bit bus, BLE goes active for all (odd or
even address) accesses. BHE will not go active during any accesses on an 8-bit bus.
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all reads and fetches, in order to meet hold
time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address changes.
3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active
4. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load capacitance
for all outputs (except ClkOut) = 80 pF.
5. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H3 User Manual for details.
6. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus,
A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch.
7. The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit. In those cases where a
maximum value is specified in the table for this parameter, it is tested.
1999 Sep 24
29