XA-H3 Datasheet, PDF (25/36 Pages) NXP Semiconductors – CMOS 16-bit highly integrated microcontroller

Philips Semiconductors
CMOS 16-bit highly integrated microcontroller
Preliminary specification
XA-H3
Table 7. UART0 Interrupts (Interrupt structure is the same except for bit locations for all 4 UARTs)
Potential
UART0
Interrupt
Individual Enable Bit
Source Bit
MMR Hex Offset MMR Hex Offset
Group Enable Bit(S)
MMR Hex Offset
Group Flag Bit
MMR Hex Offset
Master Enable Bit
MMR Hex Offset
Rx Character Available –
RR0[0]
820[0]
WR1[4:3]
802[4:3]
Even Channel Rx IP
RR3[5]
826[5]
UART0/1 Master
Interrupt Enable
WR9[3]
812[3]
CRC/Framing Error
Rx Overrun
Parity Error
Tx Buffer Empty
Break/Abort
Tx Underrun/EOM
CTS
–
–
WR1[2]
802[2]
See WR1[1]
RR1[6]
822[6]
RR1[5]
822[5]
RR1[4]
822[4]
RR0[2]
820[2]
Break/
Abort IE
WR15[7]
81E[7]
Tx Underrun/EOM IE
WR15[6]
81E[6]
CTS IE
WR15[5]
81E[5]
RR0[7]
820[7]
RR0[6]
820[6]
RR0[5]
820[5]
Tx Interrupt Enable
WR1[1]
802[1]
Master External/Status
Interrupt Enable
WR1[0]
802[0]
Even Channel Tx IP
RR3[4]
826[4]
Even Channel
External/Status IP
RR3[3]
826[3]
DCD
Zero Count
DCD IE
WR15[3]
81E[3]
Zero Count IE
WR15[1]
81E[1]
RR0[3]
820[3]
RR0[1]
820[1]
EXCEPTION/TRAPS PRECEDENCE
Description
Reset (h/w, watchdog, s/w)
Break Point
Trace
Stack Overflow
Divide by 0
User RETI
TRAP 0–15 (software)
Vector Address
0000–0003
0004–0007
0008–000B
000C–000F
0010–0013
0014–0017
0040–007F
Arbitration Ranking
0 (High)
1
1
1
1
1
1
1999 Sep 24
25