TM-1300 Datasheet, PDF (62/533 Pages) NXP Semiconductors – Programmable Media Processor

TM1300 Data Book
Philips Semiconductors
MMIO_BASE
offset:
0x10 3038 INT_CTL (r/w)
31
27
23
19
15
11
7
IS[D:A]
IE[D:A]
INT[D:A]
Figure 3-9. Host interrupt control register
3
0
Table 3-10. Interrupt source assignments
SOURCE
NAME
SRC
NUM
MODE SOURCE DESCRIPTION
PCI INTA
PCI INTB
PCI INTC
PCI INTD
TRI_USERIRQ
TIMER1
TIMER2
TIMER3
SYSTIMER
VIDEOIN
VIDEOOUT
AUDIOIN
AUDIOOUT
ICP
VLD
SSI
PCI
IIC
JTAG
t.b.d.
SPDO
t.b.d.
HOSTCOM
APP
DEBUGGER
RTOS
0 level
1 level
2 level
3 level
4 either
5 edge
6 edge
7 edge
8 edge
9 level
10 level
11 level
12 level
13 level
14 level
15 level
16 level
17 level
18 level
19..24
25 level
26..27
28 edge
29 edge
30 edge
31 edge
PCI_INTA# pin signal
PCI_INTB# pin signal
PCI_INTC# pin signal
PCI_INTD# pin signal
external general-purpose
pin
general-purpose timer
general-purpose timer
general-purpose timer
reserved for debugger
video in block
video out block
audio in block
audio out block
image coprocessor
VLD coprocessor
SSI interface
PCI BIU (DMA, etc.; see
Table 11-14 for possible
interrupt causes)
I²C interface
JTAG interface
reserved for future devices
SPDO block
reserved for future devices
(software) host communica-
tion
(software) application
(software) debugger
(software) RTOS
rent actual state of the pins. Note that the pins have neg-
ative logic (active low) polarity and are of the open
collector output type. Hence the pin voltage is low (ac-
tive) when the logical value set or seen in the INT_CTL
register is a ‘1’.
The assertion and de-assertion of host interrupts is the
responsibility of TM1300 software.
See also Section 11.7.17, “INT_CTL Register.”
3.7 HOST TO TM1300 INTERRUPTS
A host CPU can generate an interrupt to TM1300 in sev-
eral ways:
• by a PCI MMIO write to IPENDING to assert the
HOSTCOMM interrupt (bit 28)
• by a hardware circuit that asserts one of the interrupt
request pins TRI_USERIRQ, or INTA..INTD.
The first and most common method requires no circuitry
and leaves the interrupt pins available for other purposes.
3.8 TIMERS
The DSPCPU contains four programmable timer/
counters, all with the same function. The first three
(TIMER1, TIMER2, TIMER3) are intended for general
use. The fourth timer/counter (SYSTIMER) is reserved
for use by the system software and should not be used
by applications.
Each timer has three registers as shown in Figure 3-10.
The MMIO register addresses shown are offset address-
es with respect to the timer’s base address.
Each timer/counter can be set to count one of the event
types specified in Table 3-12. Note that the
DATABREAK event is special, in that the timer/counter
may increment by zero, one or two in each clock cycle.
For all other event types, increments are by zero or one.
The CACHE1 and CACHE2 events serve as cache per-
formance monitoring support. The actual event selected
for CACHE1 and CACHE2 is determined by the
MEM_EVENTS MMIO register, see Section 5.7, “Perfor-
mance Evaluation Support.” If a TM1300 pin signal (VI-
CLK, etc.) is selected as an event, positive-going edges
on the signal are counted.
Each timer increments its value until the modulus is
reached. On the clock cycle where the incremented val-
ue would equal or exceed the modulus, the value wraps
around to zero or one (in the case of an increment by
two), and an interrupt is generated as defined in
Table 3-10. The timer interrupt source mode should be
set as edge-sensitive. No software interrupt acknowl-
edge to the timer device is necessary.
Counting starts and continues as long as the run bit is
set.
Loading a new modulus does not affect the contents of
the value register. If a store operation to either the mod-
ulus or value register results in value and modulus being
the same, no interrupt will be generated. If the run bit is
set, the next value will be modulus+1 or modulus+2, and
3-12
PRODUCT SPECIFICATION