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| TM-1300 Datasheet, PDF (345/533 Pages) NXP Semiconductors – Programmable Media Processor | |||
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Philips Semiconductors
Floating-point square root
DSPCPU Operations for TM1300
fsqrt
SYNTAX
[ IF rguard ] fsqrt rsrc1 â rdest
FUNCTION
if rguard then
rdest â square_root(rsrc1)
ATTRIBUTES
Function unit
Operation code
Number of operands
Modiï¬er
Modiï¬er range
Latency
Recovery
Issue slots
ftough
110
1
No
â
17
16
2
SEE ALSO
fsqrtflags readpcsw
writepcsw
DESCRIPTION
The fsqrt operation computes the squareroot of rsrc1 and stores the result into rdest. All values are in IEEE
single-precision ï¬oating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument
is denormalized, zero is substituted for the argument before computing the squareroot, and the IFZ ï¬ag in the PCSW
is set. If the result is denormalized, the result is set to zero instead, and the OFZ ï¬ag in the PCSW is set. If fsqrt
causes an IEEE exception, the corresponding exception ï¬ags in the PCSW are set. The PCSW exception ï¬ags are
sticky: the ï¬ags can be set as a side-effect of any ï¬oating-point operation but can only be reset by an explicit
writepcsw operation. The update of the PCSW exception ï¬ags occurs at the same time as rdest is written. If any
other ï¬oating-point compute operations update the PCSW at the same time, the net result in each exception ï¬ag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception ï¬ag.
The fsqrtflags operation computes the exception ï¬ags that would result from an individual fsqrt.
The fsqrt operation optionally takes a guard, speciï¬ed in rguard. If a guard is present, its LSB controls the
modiï¬cation of the destination register. If the LSB of rguard is 1, rdest and the exception ï¬ags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception ï¬ags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (â3.0)
r40 = 0x40400000 (3.0)
r10 = 0, r40 = 0x40400000 (3.0)
r20 = 1, r40 = 0x40400000 (3.0)
r82 = 0x00c00000 (1.763241526eâ38)
r84 = 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00400000 (5.877471754e-39)
fsqrt r60 â r90
fsqrt r40 â r95
IF r10 fsqrt r40 â r100
IF r20 fsqrt r40 â r110
fsqrt r82 â r112
fsqrt r84 â r113
fsqrt r70 â r120
fsqrt r80 â r125
r90 â 0xffffffff (QNaN), INV ï¬ag set
r95 â 0x3fddb3d7 (1.732051), INX ï¬ag set
no change, since guard is false
r110 â 0x3fddb3d7 (1.732051), INX ï¬ag set
r112 â 0x201cc471 (1.32787105e-19), INX ï¬ag set
r113 â 0x7f800000 (+INF)
r120 â 0x5f7fffff (1.8446743e19), INX ï¬ag set
r125 â 0, IFZ ï¬ag set
PRODUCT SPECIFICATION
A-59
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