TM-1300 Datasheet, PDF (180/533 Pages) NXP Semiconductors – Programmable Media Processor

TM1300 Data Book
The benefit of on-chip interleaving is sustainable full-
bandwidth data transfer (1 word per clock cycle). The
transition from one internal bank to the other happens on
8-word boundaries; transferring 8 words gives the inac-
tive bank time to prepare (perform precharge, RAS, and
CAS) so that when the last word of the 8-word block in
the active bank has been transferred, the next word from
the just-precharged bank is ready on the next cycle.
The seamless transitions between the two on-chip banks
can be sustained for a stream of contiguous addresses
with the same direction (read or write). That is, a stream
of contiguous reads or contiguous writes can sustain full
bandwidth. If a write follows a read, then a small gap be-
tween transfers is needed.
Each bank access is terminated with a read or write with
automatic precharge, making a separate precharge
command before the next RAS unnecessary.
12.11 REFRESH
The MMI performs SDRAM refresh cycles autonomously
using the CAS-before-RAS (CBR) mechanism. SDRAMs
have a 4K refresh interval: either 4096 rows must be re-
freshed every 64 ms or 2048 rows every 32 ms.
The MMI performs refresh at timed intervals: one CBR
refresh command must be issued every 15.6 µsec. A
counter in the MMI keeps track of the number of SDRAM
clock cycles between refresh operations. This counter
starts after the CBR operation has completed; this CBR
operation take 19 cycles. When the counter reaches a
programmed limit, the next refresh operation is due, and
the next-in-line data transfer request from the data-high-
way is delayed until the CBR operation is executed.
All devices in the main-memory system are refreshed si-
multaneously. The REFRESH field in the MM_CONFIG
register determines the number of memory-system clock
cycles (as distinguished from TM1300 core clock cycles)
between the CBR refresh operations. Table 12-10 lists
the number of memory-system clocks for typical SDRAM
operation speeds.
Table 12-10. Refresh Intervals
SDRAM Operation Speed
100 MHz
125 MHz
133 MHz
143 MHz
Value For REFRESH Field
(decimal)
1540
1930
2060
2210
Each CBR refresh operation takes 19 SDRAM clock cy-
cles. Thus, at 100-MHz, refresh consumes about 1.2% of
maximum available SDRAM bandwidth (19 cycles out of
1560). The bandwidth impact is slightly higher at lower
frequencies.
Philips Semiconductors
12.12 POWER-DOWN MODE
When TM1300TM1300 is put into power-down mode to
reduce power consumption, the MMI responds by putting
the SDRAM devices into their power-down mode. In this
mode, the SDRAM devices retain their contents through
self-refresh.
12.13 OUTPUT DRIVER CAPACITY
TM1300’s output driver circuits for the memory address
and control signals (output signals in Table 12-7), can
drive up to four memory devices when the memory inter-
face is operating at 143 MHz. If more devices are con-
nected, then a lower SDRAM clock frequency must be
chosen.
Table 12-11 lists the clock frequency as a function of the
number of memory devices connected to unbuffered
memory interface signals.
Two identical outputs are provided for both the MM_CKE
(clock-enable) and MM_CLK signals. Each MM_CKE
and MM_CLK signal is capable of driving two SDRAM
devices at 143 MHz, thus the total of four devices.
12.14 SIGNAL PROPAGATION DELAY
COMPENSATION
The TM1300 MMI no longer has the two special pins,
MM_MATCHOUT and MM_MATCHIN, that were used in
the TM1100 and TM1000. This loop helped the interface
compensate for the propagation delay through circuit-
board traces to and from the external SDRAM devices. It
is now integrated into the MMI. Read timing is internally
derived.
To avoid excessive ringing of the clock signals, series
termination with a 33-ohm resistor is advised at the clock
outputs.
The delay of the memory clock with respect to the inter-
nal sending and receiving clocks is adjusted inside the
memory interface to achieve reliable communication and
guarantee correct setup and hold times.
Figure 12-4 shows a conceptual circuit board layout.
Two SDRAM devices share a single clock output. The
clock signals should have source-series termination.
12.15 CIRCUIT BOARD DESIGN
TM1300 and its memory array form a high-speed digital
system. Even though only a small number of chips is in-
volved, this digital system operates at frequencies high
enough to make the analog characteristics of the con-
nections between the chips significant. Consequently,
the system designer must take care to ensure reliable
operation.
12.15.1 General Guidelines
• In general, TM1300 and its memory chips should be
as close together as possible to minimize parasitic
12-6
PRODUCT SPECIFICATION