TM-1300 Datasheet, PDF (136/533 Pages) NXP Semiconductors – Programmable Media Processor

TM1300 Data Book
• set AI_FREQ to ensure that a valid clock is gener-
ated (Only when AI is the master of the audio clock
system)
• MMIO(AI_CTL) = 1 << 31; /* Software Reset */
• MMIO(AI_SERIAL) = 1 << 31; /* sets serial-master
mode, starts AI_SCK */
• MMIO(AI_SERIAL) = (1 << 31) | (SCKDIV value); /*
then set DIVIDER values */
The DSPCPU initiates capture by providing two equal
size empty buffers and putting their base address and
size in the BASE_n and SIZE registers. Once two valid (lo-
cal memory) buffers are assigned, capture can be en-
abled by writing a ‘1’ to CAP_ENABLE. The AI unit hard-
ware now proceeds to fill buffer 1 with input samples.
Once buffer 1 fills up, BUF1_FULL is asserted, and cap-
ture continues without interruption in buffer 2. If
BUF1_INTEN is enabled, a SOURCE 11 interrupt re-
quest is generated.
Note that the buffers must be 64-byte aligned, and a mul-
tiple of 64 samples in size (the six LSBs of AI_BASE1,
AI_BASE2 and AI_SIZE are always ’0’).
The DSPCPU is required to assign a new, empty buffer
to BASE1 and perform an ACK1, before buffer 2 fills up.
Capture continues in buffer 2, until it fills up. At that time,
BUF2_FULL is asserted, and capture continues in the
new buffer 1, etc.
Upon receipt of an ACK, the AI hardware removes the re-
lated interrupt request line assertion at the next DSPCPU
clock edge. Refer to Section 3.5.3, “INT and NMI
(Maskable and Non-Maskable Interrupts),” for the rules
regarding ACK and interrupt re-enabling. The AI interrupt
should always be operated in level-sensitive mode, since
AI can signal multiple conditions that each need indepen-
dent ACKs over the single internal SOURCE 11 request
line.
In normal operation, the DSPCPU and AI hardware con-
tinuously exchange buffers without ever loosing a sam-
ple. If the DSPCPU fails to provide a new buffer in time,
the OVERRUN error flag is raised. This flag is not affect-
ed by ACK1 or ACK2; it can only be cleared by an explicit
ACK_OVR.
8.8 POWER DOWN AND SLEEPLESS
The AI unit enters power down state whenever TM1300
is put in global power down mode, except if the SLEEP-
LESS bit in AI_CTL is set. In the latter case, the unit con-
tinues DMA operation and will wake up the DSPCPU
whenever an interrupt is generated.
The AI unit can be separately powered down by setting
a bit in the BLOCK_POWER_DOWN register. Refer to
Chapter 21, “Power Management.”
It is recommended that AI be stopped (by negating
AI_CTL.CAP_ENABLE) before block level power down
is started, or that SLEEPLESS mode is used when global
power down is activated.
Philips Semiconductors
8.9 HIGHWAY LATENCY AND HBE
The AI unit uses internal buffering before writing data to
SDRAM. The internal buffer consists of one stereo sam-
ple input holding register and 64 bytes of internal buffer
memory. Under normal operation, the 64-byte buffer is
written to SDRAM while the input register receives an-
other sample. This normal operation is guaranteed to be
maintained as long as the highway arbiter is set to guar-
antee a latency for the AI unit that matches the sampling
interval. Given a sample rate f_s, and an associated sam-
ple interval T (in nsec), the arbiter should be set to have
a latency of at most T-20 nsec. Refer to Chapter 20, “Ar-
biter,” for information on arbiter programming. If the re-
quested latency is not adequate, the HBE (Highway
Bandwidth Error) condition may result. This error flag
gets set when the input register is full, the 64-byte buffer
has not yet been written to memory, and a new sample
arrives.
Table 8-7 shows the required arbiter latency settings for
Table 8-7. AI highway arbiter latency requirement
examples
CapMode
stereo
16 bits/sample
stereo
16 bits/sample
stereo
16 bits/sample
f_s
(kHz)
44.1
48.0
96.0
T
(nS)
22,676
20,833
10,417
max
arbiter
latency
(nsec)
access pattern
22,656
20,813
10,397
1 request every
362,812 nsec
1 request every
333,333 nsec
1 request every
166,667 nsec
a number of common operating modes. The rightmost
column illustrates the nature of the resulting 64-byte
highway requests. Is not necessary to compute arbiter
settings, but they may be used to compute bus availabil-
ity in a given interval.
Table 8-8. AI MMIO status fields (read only)
Field Name
Description
BUF1_ACTIVE
• If ‘1’, buffer 1 will be used for the next
incoming sample. If ‘0’, buffer 2 will receive
the next sample.
• 1 after RESET.
BUF1_FULL
• If ‘1’, buffer 1 is full. If BUF1_INTEN is also
‘1’, an interrupt request (source 11) is
pending. BUF1_FULL is cleared by writing
a ‘1’ to ACK1, at which point the AI hard-
ware will assume that BASE1 and SIZE
describe a new empty buffer.
• 0 after RESET.
8-6
PRODUCT SPECIFICATION