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TM-1300 Datasheet, PDF (339/533 Pages) NXP Semiconductors – Programmable Media Processor | |||
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Philips Semiconductors
Floating-point multiply
DSPCPU Operations for TM1300
fmul
SYNTAX
[ IF rguard ] fmul rsrc1 rsrc2 â rdest
FUNCTION
if rguard then
rdest â (ï¬oat)rsrc1 à (ï¬oat)rsrc2
ATTRIBUTES
Function unit
Operation code
Number of operands
Modiï¬er
Modiï¬er range
Latency
Issue slots
ifmul
28
2
No
â
3
2, 3
SEE ALSO
imul umul dspimul
dspidualmul fmulflags
readpcsw writepcsw
DESCRIPTION
The fmul operation computes the product rsrc1Ãrsrc2 and stores the result into rdest. All values are in IEEE single-
precision ï¬oating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
denormalized, zero is substituted for the argument before computing the product, and the IFZ ï¬ag in the PCSW is set.
If the result is denormalized, the result is set to zero instead, and the OFZ ï¬ag in the PCSW is set. If fmul causes an
IEEE exception, the corresponding exception ï¬ags in the PCSW are set. The PCSW exception ï¬ags are sticky: the
ï¬ags can be set as a side-effect of any ï¬oating-point operation but can only be reset by an explicit writepcsw
operation. The update of the PCSW exception ï¬ags occurs at the same time as rdest is written. If any other ï¬oating-
point compute operations update the PCSW at the same time, the net result in each exception ï¬ag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception ï¬ag.
The fmulflags operation computes the exception ï¬ags that would result from an individual fmul.
The fmul operation optionally takes a guard, speciï¬ed in rguard. If a guard is present, its LSB controls the
modiï¬cation of the destination register. If the LSB of rguard is 1, rdest and the exception ï¬ags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception ï¬ags in PCSW.
EXAMPLES
Initial Values
r60 = 0xc0400000 (â3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (â3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435eâ38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435eâ38)
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435eâ38)
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754eâ39)
r82 = 0x00c00000 (1.763241526eâ38),
r83 = 0x8080000 (â1.175494351eâ38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (âINF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526eâ38)
Operation
fmul r60 r30 â r90
Result
r90 â 0xc0400000 (-3.0)
fmul r40 r60 â r95
r95 â 0xc1100000 (-9.0)
IF r10 fmul r40 r80 â r100 no change, since guard is false
IF r20 fmul r40 r80 â r105 r105 â 0x1400000 (3.52648305e-38)
fmul r41 r80 â r110
r110 â 0x0, OFZ, UNF, INX ï¬ags set
fmul r42 r43 â r106
r106 â 0xffffffff (QNaN), INV ï¬ag set
fmul r40 r81 â r111
r111 â 0, IFZ ï¬ag set
fmul r82 r83 â r112
r112 â 0, UNF, INX ï¬ag set
fmul r84 r85 â r113
r113 â 0xff800000 (-INF)
fmul r70 r70 â r120
fmul r80 r80 â r125
r120 â 0x7f800000, OVF, INX ï¬ags set
r125 â 0, UNF, INX ï¬ag set
PRODUCT SPECIFICATION
A-53
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