TDA8357J Datasheet, PDF(6/16 Page) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS

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TDA8357J Datasheet, PDF (6/16 Pages) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS

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Philips Semiconductors

Full bridge vertical deï¬ection output circuit

in LVDMOS

Preliminary speciï¬cation

TDA8357J

CHARACTERISTICS

VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 Â°C; measured in test circuit of Fig.3; unless otherwise

speciï¬ed.

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Supplies

VFB

Iq(P)(av)

Iq(P)

Iq(FB)(av)

operating supply voltage

ï¬yback supply voltage

average quiescent supply current

quiescent supply current

average quiescent ï¬yback supply

current

note 1

during scan

no signal; no load

during scan

7.5 12

2VP 45

Inputs A and B

Vi(dif)(p-p) differential input voltage

note 2

(peak-to-peak value)

VI(bias)

input bias voltage

note 2

100

II(bias)

input bias current

Outputs A and B

Vloss(1)

Vloss(2)

Io(p-p)

voltage loss ï¬rst scan part

voltage loss second scan part

output current (peak-to-peak value)

linearity error

note 3

Io = 0.7 A

Io = 1.0 A

note 4

Io = â0.7 A

Io = â1.0 A

Io(p-p) = 2.0 A; notes 5 and 6

adjacent blocks

non adjacent blocks

Voffset

offset voltage

across RM; Vi(dif) = 0 V

VI(bias) = 200 mV

VI(bias) = 1 V

âVoffset(T) offset voltage variation with temperature across RM; Vi(dif) = 0 V

DC output voltage

Vi(dif) = 0 V

Gv(ol)

open-loop voltage gain

notes 7 and 8

fâ3dB(h)

high â3 dB cut-off frequency

open-loop

voltage gain

note 9

âGv(T)

voltage gain variation with the

temperature

PSRR

power supply rejection ratio

note 10

1000 1500 mV

880 1600 mV

ÂµA

3.9 V

5.5 V

2.8 V

4.0 V

2.0 A

0.5VP

Â±15

Â±25

10â4

ÂµV/K

kHz

Kâ1

1999 Nov 10

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