TDA8357J Datasheet, PDF (4/16 Pages) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS

Philips Semiconductors
Full bridge vertical deflection output circuit
in LVDMOS
Preliminary specification
TDA8357J
FUNCTIONAL DESCRIPTION
Vertical output stage
The vertical driver circuit has a bridge configuration.
The deflection coil is connected between the
complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially
designed for direct connection to driver circuits delivering
a differential signal but it is also suitable for single-ended
applications. The output currents of the driver device are
converted to voltages by the conversion resistors
R_CV1 and R_CV2 (see Fig.3) connected to pins INA
and INB. The differential input voltage is compared with
the voltage across the measuring resistor R_M, providing
internal feedback information. The voltage across R_M is
proportional with the output current. The relationship
between the differential input current and the output
current is defined by:
2 × I_i(dif)(p-p) × R_CV = I_o(p-p) × R_M
The output current should measure 0.5 to 2.0 A (p-p) and
is determined by the value of R_M and R_CV. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of R_M and the
internal bondwire resistance (typical value of 50 mΩ) the
actual value of the current in the deflection coil will be
about 5% lower than calculated.
Flyback supply
The flyback voltage is determined by the flyback supply
voltage V_FB. The principle of two supply voltages (class G)
allows to use an optimum supply voltage V_P for scan and
an optimum flyback supply voltage V_FB for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to V_FB, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise
and fall times of the flyback switch are determined mainly
by the slew-rate value of more than 300 V/µs.
Guard circuit
A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:
• During thermal protection (T_j ≈ 170 °C)
• During an open-loop condition.
The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.
Damping resistor compensation
HF loop stability is achieved by connecting a damping
resistor R_D1 across the deflection coil. The current values
in R_D1 during scan and flyback are significantly different.
Both the resistor current and the deflection coil current flow
into measuring resistor R_M, resulting in a too low deflection
coil current at the start of the scan.
The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time.
For that purpose a compensation resistor R_CMP in series
with a zener diode is connected between pins OUTA
and INA (see Fig.4). The zener diode voltage value should
be equal to V_P. The value of R_CMP is calculated by:
R_CMP = ₍---V----_F⁽---V_B----^F-_–--^B--V---^–--_l-_o-V--_s--^ls--^o-₍--^sF--^s-_B--⁽-₎-^F--_–-^B---⁾-I--_c^–--_o---V_i--_l-₍-^Z-_p--⁾-_e--_a-^×--_k--R-₎---_×-^D----¹_R----^×_c---_o-R--_i-_l-₎-^C---_×-^V---¹-R----_M---
where:
• V_loss(FB) is the voltage loss between pins V_FB and OUTA
at flyback
• R_coil is the deflection coil resistance
• V_Z is the voltage of zener diode D5.
Protection
The output circuit contains protection circuits for:
• Too high die temperature
• Overvoltage of output A.
1999 Nov 10
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