TDA8357J Datasheet, PDF (3/16 Pages) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS

Philips Semiconductors
Full bridge vertical deflection output circuit
in LVDMOS
Preliminary specification
TDA8357J
BLOCK DIAGRAM
handbook, full pagewidth
VI(bias)
0
Vi(p-p)
VI(bias)
0
Vi(p-p)
GUARD
VP
VFB
8
GUARD
CIRCUIT
INA 1
INPUT
AND
FEEDBACK
CIRCUIT
INB ₂
3
6
M2
D1
M4
M5
D3
D2
7 ^OUTA
9
FEEDB
M1
4 OUTB
M3
TDA8357J
5
GND
Fig.1 Block diagram.
MGS803
PINNING
SYMBOL
INA
INB
V_P
OUTB
GND
V_FB
OUTA
GUARD
FEEDB
PIN
DESCRIPTION
1
input A
2
input B
3
supply voltage
4
output B
handbook, halfpage
INA 1
INB 2
VP 3
OUTB 4
5
ground
GND 5 _TDA8357J
6
flyback supply voltage
VFB 6
7
output A
8
guard output
9
feedback input
OUTA 7
GUARD 8
FEEDB 9
MGS804
The exposed die pad is connected to pin GND.
Fig.2 Pin configuration.
1999 Nov 10
3