TDA8357J Datasheet, PDF (5/16 Pages) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS

Philips Semiconductors
Full bridge vertical deflection output circuit
in LVDMOS
Preliminary specification
TDA8357J
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
V_P
supply voltage
V_FB
flyback supply voltage
V_n
DC voltage
pin OUTA
pin OUTB
pins INA, INB, GUARD and FEEDB
I_n
DC current
pins OUTA and OUTB
pins OUTA and OUTB
pins INA, INB, GUARD and FEEDB
I_lu
latch-up current
V_es
P_tot
T_stg
T_amb
T_j
electrostatic handling voltage
total power dissipation
storage temperature
ambient temperature
junction temperature
CONDITIONS
MIN.
−
−
MAX. UNIT
18
V
68
V
note 1
−
68
V
−
V_P
V
−0.5 V_P
V
during scan (p-p)
−
2.0 A
at flyback (peak); t ≤ 1.5 ms
−
±1.2 A
−20 +20 mA
current into any pin; pin voltage −
is 1.5 × V_P; note 2
+200 mA
current out of any pin; pin voltage −200 −
mA
is −1.5 × V_P; note 2
machine model; note 3
−300 +300 V
human body model; note 4
−2000 +2000 V
−
8
W
−55 +150 °C
−25 +75 °C
note 5
−
150 °C
Notes
1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.
2. At T_j(max).
3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.
4. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.
5. Internally limited by thermal protection at T_j ≈ 170 °C.
THERMAL CHARACTERISTICS
In accordance with IEC 747-1.
SYMBOL
PARAMETER
R_th(j-c)
R_th(j-a)
thermal resistance from junction to case
thermal resistance from junction to ambient
CONDITIONS
in free air
MIN.
−
−
TYP.
−
−
MAX. UNIT
6
K/W
65
K/W
1999 Nov 10
5