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PSMN8R5-60YS_15 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel LFPAK 60 V, 8 mΩ standard level MOSFET
NXP Semiconductors
PSMN8R5-60YS
N-channel LFPAK 60 V, 8 mΩ standard level MOSFET
Symbol
Parameter
Conditions
Dynamic characteristics
QG(tot)
total gate charge
ID = 60 A; VDS = 30 V; VGS = 10 V;
Fig. 14; Fig. 15
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
gate-source charge
ID = 60 A; VDS = 30 V; VGS = 10 V;
Fig. 15; Fig. 14
QGS(th)
pre-threshold gate-
source charge
ID = 60 A; VDS = 30 V; VGS = 10 V;
Fig. 14
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
ID = 60 A; VDS = 30 V; VGS = 10 V;
Fig. 15; Fig. 14
VGS(pl)
gate-source plateau
voltage
VDS = 30 V; Fig. 14; Fig. 15
Ciss
input capacitance
VDS = 30 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 30 V; RL = 0.5 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VSD
source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 30 V
Min Typ Max Unit
-
39
-
nC
-
33
-
nC
-
13.3 -
nC
-
7
-
nC
-
6.2 -
nC
-
7.7 -
nC
-
5.2 -
V
-
2370 -
pF
-
307 -
pF
-
172 -
pF
-
18.4 -
ns
-
13.7 -
ns
-
32.4 -
ns
-
9.2 -
ns
-
0.8 1.2 V
-
43.3 -
ns
-
61.4 -
nC
PSMN8R5-60YS
Product data sheet
All information provided in this document is subject to legal disclaimers.
22 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved
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