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PSMN8R5-100PS_15 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel 100 V 8.5 mΩ standard level MOSFET in TO220
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NXP Semiconductors
PSMN8R5-100PS
N-channel 100 V 8.5 mΩ standard level MOSFET in TO220
Symbol
Parameter
Conditions
Dynamic characteristics
QG(tot)
QGS
total gate charge
gate-source charge
ID = 25 A; VDS = 50 V; VGS = 10 V;
Fig. 14; Fig. 15
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 15 A; VDS = 50 V; Fig. 14; Fig. 15
Ciss
input capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16; Fig. 17
Coss
output capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 17
Crss
reverse transfer
VDS = 50 V; VGS = 0 V; f = 1 MHz;
capacitance
Tj = 25 °C; Fig. 16; Fig. 17
td(on)
tr
turn-on delay time
rise time
VDS = 50 V; RL = 2 Ω; VGS = 10 V;
RG(ext) = 5 Ω
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 18
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 50 V
Min Typ Max Unit
-
111 -
nC
-
24
-
nC
-
16
-
nC
-
8
-
nC
-
33
-
nC
-
4.4 -
V
-
5512 -
pF
-
380 -
pF
-
256 -
pF
-
20
-
ns
-
35
-
ns
-
87
-
ns
-
43
-
ns
-
0.82 1.2 V
-
53
-
ns
-
124 -
nC
PSMN8R5-100PS
Product data sheet
All information provided in this document is subject to legal disclaimers.
17 October 2013
© NXP N.V. 2013. All rights reserved
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