PSMN8R0-30YL_1105 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

NXP Semiconductors
PSMN8R0-30YL
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK
Table 6. Characteristics …continued
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Source-drain diode
V_SD
source-drain voltage
I_S = 25 A; V_GS = 0 V; T_j = 25 °C;
see Figure 16
t_rr
reverse recovery time
I_S = 15 A; dI_S/dt = -100 A/µs;
Q_r
recovered charge
V_GS = 0 V; V_DS = 15 V
80
I_D
V_GS(V) = 10
4.5
(A)
60
003aaf421
3.5
60
I_D
(A)
45
Min Typ Max Unit
-
0.9 1.2 V
-
34
-
ns
-
30
-
nC
003aaf422
40
3.0
2.8
20
2.6
2.4
0
0
0.5
1
1.5
2
V_DS(V)
30
T_j = 150 °C T_j = 25 °C
15
0
0
1
2
3
4
5
V_GS(V)
Fig 5. Output characteristics: drain current as a
Fig 6. Transfer characteristics: drain current as a
function of drain-source voltage; typical values
function of gate-source voltage; typical values
003aaf423
003aaf424
60
2000
g_fs
C
(S)
(pF)
C_iss
45
1500
C_rss
30
1000
15
500
0
0
15
30
45
60
I_D (A)
0
0
3
6
9
12
V_GS(V)
Fig 7. Forward transconductance as a function of
drain current; typical values
Fig 8. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
PSMN8R0-30YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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