PSMN8R0-30YL_1105 Datasheet, PDF (1/14 Pages) NXP Semiconductors – N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

PSMN8R0-30YL
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK
Rev. 2 — 16 May 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
„ High efficiency due to low switching
and conduction losses
„ Suitable for logic level gate drive
sources
1.3 Applications
„ Class-D amplifiers
„ DC-to-DC converters
„ Motor control
„ Server power supplies
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
V_DS
drain-source
voltage
T_j ≥ 25 °C; T_j ≤ 175 °C
I_D
drain current
T_mb = 25 °C; V_GS = 10 V;
see Figure 1
P_tot
total power
dissipation
T_mb = 25 °C; see Figure 2
Static characteristics
R_DSon
drain-source
V_GS = 10 V; I_D = 15 A; T_j = 25 °C
on-state resistance
Dynamic characteristics
Q_GD
gate-drain charge V_GS = 10 V; I_D = 45 A; V_DS = 15 V;
see Figure 14; see Figure 15
Q_G(tot)
total gate charge
V_GS = 4.5 V; I_D = 45 A; V_DS = 15 V;
see Figure 14; see Figure 15
Avalanche ruggedness
E_DS(AL)S
non-repetitive
drain-source
avalanche energy
V_GS = 10 V; T_j(init) = 25 °C;
I_D = 62 A; V_sup ≤ 30 V; R_GS = 50 Ω;
unclamped
Min Typ Max Unit
-
-
30 V
-
-
62 A
-
-
56 W
-
6.9 8.3 mΩ
-
4-
nC
-
9-
nC
-
-
21 mJ