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| PSMN038-100YL_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel 100 V 37.5 mΩ logic level MOSFET in LFPAK56 | |||
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NXP Semiconductors
PSMN038-100YL
N-channel 100 V 37.5 mΩ logic level MOSFET in LFPAK56
Symbol
Parameter
Conditions
Dynamic characteristics
QG(tot)
total gate charge
ID = 5 A; VDS = 80 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
ID = 5 A; VDS = 80 V; VGS = 5 V;
Tj = 25 °C; Fig. 14; Fig. 15
QGS
gate-source charge
ID = 5 A; VDS = 80 V; VGS = 10 V;
QGD
gate-drain charge
Tj = 25 °C; Fig. 14; Fig. 15
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
VGS(pl)
gate-source plateau
voltage
ID = 5 A; VDS = 80 V; Tj = 25 °C;
Fig. 14; Fig. 15
Ciss
input capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 80 V; RL = 10 Ω; VGS = 5 V;
RG(ext) = 5 Ω; Tj = 25 °C
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VSD
source-drain voltage IS = 5 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 25 V; Tj = 25 °C
Min Typ Max Unit
-
39.2 -
nC
-
21.6 -
nC
-
3.8 -
nC
-
8.3 -
nC
-
2.7 -
nC
-
1.1 -
nC
-
2.3 -
V
-
1905 -
pF
-
137 -
pF
-
90
-
pF
-
10
-
ns
-
18
-
ns
-
31
-
ns
-
18
-
ns
-
0.78 1.2 V
-
31
-
ns
-
44
-
nC
PSMN038-100YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
1 May 2013
© NXP B.V. 2013. All rights reserved
6 / 13
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