PHU2N50E Datasheet, PDF (6/9 Pages) NXP Semiconductors – PowerMOS transistors Avalanche energy rated

Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHU2N50E
Gate-Source voltage, VGS (Volts)
20
ID = 2 A
300 V
200 V
15
PHP2N50
VDD = 400 V
10
5
0
0
10
20
30
40
Gate charge, Qg (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); parameter V_DS
Switching times, td(on), tr, td(off), tf (ns)
1000
VDD = 250V
RD = 120 Ohms
Tj = 25 C
100
td(off)
PHP2N50
10
tr
tf
td(on)
1
0
20
40
60
80
100
Gate resistance, RG (Ohms)
Fig.14. Typical switching times; t_d(on), t_r, t_d(off), t_f = f(R_G)
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage;
V_(BR)DSS/V_{(BR)DSS 25 ˚C} = f(T_j)
Source-drain diode current, IF(A)
10
VGS = 0 V
8
150 C
6
PHP2N50
Tj = 25 C
4
2
0
0
0.5
1
1.5
Source-Drain voltage, VSDS (V)
Fig.16. Source-Drain diode characteristic.
I_F = f(V_SDS); parameter T_j
Non-repetitive Avalanche current, IAS (A)
10
Tj prior to avalanche = 25 C
1
VDS
0.1
ID
0.01
1E-06
125 C
tp
PHP2N50E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.17. Maximum permissible non-repetitive
avalanche current (I_AS) versus avalanche time (t_p);
unclamped inductive load
Maximum Repetitive Avalanche Current, IAR (A)
10
1
Tj prior to avalanche = 25 C
0.1
125 C
0.01
0.001
1E-06
PHP2N50E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.18. Maximum permissible repetitive avalanche
current (I_AR) versus avalanche time (t_p)
May 1999
6
Rev 1.000