80C51 Datasheet, PDF (6/38 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
Product specification
80C51/87C51/80C31
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION
V_SS
V_CC
P0.0–0.7
20
40
39–32
22
44
43–36
16
38
37–30
I Ground: 0V reference.
I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification and received code bytes during EPROM
programming. External pull-ups are required during program verification.
P1.0–P1.7
1–8 2–9 40–44, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
1–3
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I_IL). Port 1 also receives the low-order address byte
during program memory verification. Alternate functions for Port 1 include:
1
2
40
I/O
T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out).
2
3
41
I
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control.
P2.0–P2.7
21–28 24–31 18–25
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I_IL). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses
(MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins
receive the high order address bits during EPROM programming and verification.
P3.0–P3.7 10–17 11,
5,
13–19 7–13
10
11
5
11
13
7
12
14
8
13
15
9
14
16
10
15
17
11
16
18
12
17
19
13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I_IL). Port 3 also serves the special features of the 80C51
family, as listed below:
I
RxD (P3.0): Serial input port
O
TxD (P3.1): Serial output port
I
INT0 (P3.2): External interrupt
I
INT1 (P3.3): External interrupt
I
T0 (P3.4): Timer 0 external input
I
T1 (P3.5): Timer 1 external input
O
WR (P3.6): External data memory write strobe
O
RD (P3.7): External data memory read strobe
RST
9
10
4
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V_SS permits a power-on reset using only an external
capacitor to V_CC.
ALE/PROG 30
33
27
O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
PSEN
29
32
26
O Program Store Enable: The read strobe to external program memory. When the 8XC51/31
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program memory.
EA/V_PP
31
35
29
I External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H and
0FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 0FFFH. This pin also receives the
12.75V programming supply voltage (V_PP) during EPROM programming. If security bit 1 is
programmed, EA will be internally latched on Reset.
XTAL1
19
21
15
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18
20
14
O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V_CC + 0.5V or V_SS – 0.5V, respectively.
2000 Jan 20
6