80C51 Datasheet, PDF (21/38 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
Product specification
80C51/87C51/80C31
DC ELECTRICAL CHARACTERISTICS
T_amb = 0°C to +70°C or –40°C to +85°C, V_CC = 2.7V to 5.5V, V_SS = 0V (16MHz devices)
SYMBOL
PARAMETER
TEST
CONDITIONS
LIMITS
MIN
TYP¹
MAX
UNIT
V_IL
V_IH
V_IH1
V_OL
V_OL1
V_OH
V_OH1
I_IL
I_TL
Input low voltage
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, ⁸
Output low voltage, port 0, ALE, PSEN^{8, 7}
Output high voltage, ports 1, 2, 3 ³
Output high voltage (port 0 in external bus mode),
ALE⁹, PSEN³
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3⁶
4.0V < V_CC < 5.5V
2.7V<V_CC< 4.0V
V_CC = 2.7V
I_OL = 1.6mA²
V_CC = 2.7V
I_OL = 3.2mA²
V_CC = 2.7V
I_OH = –20µA
V_CC = 4.5V
I_OH = –30µA
V_CC = 2.7V
I_OH = –3.2mA
V_IN = 0.4V
V_IN = 2.0V
See note 4
–0.5
–0.5
0.2V_CC+0.9
0.7V_CC
V_CC – 0.7
V_CC – 0.7
V_CC – 0.7
–1
0.2V_CC–0.1
V
0.7
V
V_CC+0.5
V
V_CC+0.5
V
0.4
V
0.4
V
V
V
V
–50
µA
–650
µA
I_LI
Input leakage current, port 0
0.45 < V_IN < V_CC – 0.3
±10
µA
I_CC
Power supply current (see Figure 21):
Active mode @ 16MHz
See note 5
Idle mode @ 16MHz
Power-down mode or clock stopped (see Figure 25 T_amb = 0°C to 70°C
for conditions)
T_amb = –40°C to +85°C
µA
µA
3
50
µA
75
µA
R_RST
Internal reset pull-down resistor
40
225
kΩ
C_IO
Pin capacitance¹⁰ (except EA)
15
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I_OL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the V_CC–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V_IN is approximately 2V.
5. See Figures 22 through 25 for I_CC test conditions.
Active mode: I_CC = 0.9 × FREQ. + 1.1mA
Idle mode:
I_CC = 0.18 × FREQ. +1.01mA; See Figure 21.
6. This value applies to T_amb = 0°C to +70°C. For T_amb = –40°C to +85°C, I_TL = –750µA.
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OL per port pin:
15mA (*NOTE: This is 85°C specification.)
Maximum I_OL per 8-bit port:
26mA
Maximum total I_OL for all outputs: 71mA
If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to V_OH1, except when ALE is off then V_OH is the voltage specification.
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA is 25pF).
2000 Jan 20
21