80C51 Datasheet, PDF (23/38 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
Product specification
80C51/87C51/80C31
AC ELECTRICAL CHARACTERISTICS
T_amb = 0°C to +70°C or –40°C to +85°C, V_CC = +2.7V to +5.5V, V_SS = 0V^{1, 2, 3}
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t_CLCL
FIGURE
14
PARAMETER
Oscillator frequency⁵
Speed versions :S
MIN MAX
MIN
3.5
MAX
16
UNIT
MHz
t_LHLL
14
t_AVLL
14
t_LLAX
14
t_LLIV
14
t_LLPL
14
t_PLPH
14
t_PLIV
14
t_PXIX
14
t_PXIZ
14
t_AVIV ⁴
14
t_PLAZ
14
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
85
2t_CLCL–40
ns
22
t_CLCL–40
ns
32
t_CLCL–30
ns
150
4t_CLCL–100
ns
32
t_CLCL–30
ns
142
3t_CLCL–45
ns
82
3t_CLCL–105
ns
0
0
ns
37
t_CLCL–25
ns
207
5t_CLCL–105
ns
10
10
ns
t_RLRH
15, 16
t_WLWH
15, 16
t_RLDV
15, 16
t_RHDX
15, 16
t_RHDZ
15, 16
t_LLDV
15, 16
t_AVDV
15, 16
t_LLWL
15, 16
t_AVWL
15, 16
t_QVWX
15, 16
t_WHQX
15, 16
t_QVWH
16
t_RLAZ
15, 16
t_WHLH
15, 16
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
275
6t_CLCL–100
ns
275
6t_CLCL–100
ns
147
5t_CLCL–165
ns
0
0
ns
65
2t_CLCL–60
ns
350
8t_CLCL–150
ns
397
9t_CLCL–165
ns
137 239
3t_CLCL–50
3t_CLCL+50
ns
122
4t_CLCL–130
ns
13
t_CLCL–50
ns
13
t_CLCL–50
ns
287
7t_CLCL–150
ns
0
0
ns
23
103
t_CLCL–40
t_CLCL+40
ns
t_CHCX
18
t_CLCX
18
t_CLCH
18
t_CHCL
18
Shift Register
High time
Low time
Rise time
Fall time
20
20
t_CLCL–t_CLCX
ns
20
20
t_CLCL–t_CHCX
ns
20
20
ns
20
20
ns
t_XLXL
17
Serial port clock cycle time
750
12t_CLCL
ns
t_QVXH
17
Output data setup to clock rising edge
492
10t_CLCL–133
ns
t_XHQX
17
Output data hold after clock rising edge
8
2t_CLCL–117
ns
t_XHDX
17
Input data hold after clock rising edge
0
0
ns
t_XHDV
17
Clock rising edge to input data valid
492
10t_CLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0Hz.
2000 Jan 20
23