80C51 Datasheet, PDF (17/38 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
Product specification
80C51/87C51/80C31
Interrupt Priority Structure
The 8XC51 and 80C31 only have a 6-source four-level interrupt
structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)
The IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
IPH.x
IP.x
0
0
0
1
1
0
1
1
INTERRUPT PRIORITY LEVEL
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 7. Interrupt Table
SOURCE
POLLING PRIORITY
X0
1
T0
2
X1
3
T1
4
SP
5
T2
6
NOTES:
1. L = Level activated
2. T = Transition activated
REQUEST BITS
IE0
TP0
IE1
TF1
RI, TI
TF2, EXF2
HARDWARE CLEAR?
N (L)¹ Y (T)²
Y
N (L) Y (T)
Y
N
N
VECTOR ADDRESS
03H
0BH
13H
1BH
23H
2BH
IE (0A8H)
7
6
5
4
3
2
1
0
EA
—
ET2
ES
ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6
—
Not implemented. Reserved for future use.
IE.5
ET2
Timer 2 interrupt enable bit.
IE.4
ES
Serial Port interrupt enable bit.
IE.3
ET1
Timer 1 interrupt enable bit.
IE.2
EX1
External interrupt 1 enable bit.
IE.1
ET0
Timer 0 interrupt enable bit.
IE.0
EX0
External interrupt 0 enable bit.
SU00571
Figure 10. IE Registers
2000 Jan 20
17