80C51 Datasheet, PDF (10/38 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz

Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
Product specification
80C51/87C51/80C31
(MSB)
TF2
EXF2
RCLK
TCLK EXEN2
TR2
C/T2
(LSB)
CP/RL2
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Position
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
Name and Significance
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU00728
Figure 1. Timer/Counter 2 (T2CON) Control Register
OSC
÷ 12
T2 Pin
C/T2 = 0
C/T2 = 1
Transition
Detector
Control
TR2 _Capture
TL2
(8-bits)
TH2
(8-bits)
RCAP2L
RCAP2H
T2EX Pin
Control
EXEN2
Figure 2. Timer 2 in Capture Mode
TF2
EXF2
Timer 2
Interrupt
SU00066
2000 Jan 20
10