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80C51 Datasheet, PDF (24/38 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz | |||
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Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7Vâ5.5V),
low power, high speed (33 MHz)
Product specification
80C51/87C51/80C31
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or â40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
VARIABLE CLOCK4
SYMBOL FIGURE
PARAMETER
16MHz to fmax
MIN
MAX
33MHz CLOCK
MIN
MAX
UNIT
tLHLL
14
tAVLL
14
tLLAX
14
tLLIV
14
tLLPL
14
tPLPH
14
tPLIV
14
tPXIX
14
tPXIZ
14
tAVIV
14
tPLAZ
14
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
2tCLCLâ40
21
ns
tCLCLâ25
5
ns
tCLCLâ25
ns
4tCLCLâ65
55
ns
tCLCLâ25
5
ns
3tCLCLâ45
45
ns
3tCLCLâ60
30
ns
0
0
ns
tCLCLâ25
5tCLCLâ80
10
5
ns
70
ns
10
ns
tRLRH
15, 16
tWLWH
15, 16
tRLDV
15, 16
tRHDX
15, 16
tRHDZ
15, 16
tLLDV
15, 16
tAVDV
15, 16
tLLWL
15, 16
tAVWL
15, 16
tQVWX
15, 16
tWHQX
15, 16
tQVWH
16
tRLAZ
15, 16
tWHLH
15, 16
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6tCLCLâ100
82
ns
6tCLCLâ100
82
ns
5tCLCLâ90
60
ns
0
0
ns
2tCLCLâ28
32
ns
8tCLCLâ150
90
ns
9tCLCLâ165
105
ns
3tCLCLâ50
3tCLCL+50
40
140
ns
4tCLCLâ75
45
ns
tCLCLâ30
0
ns
tCLCLâ25
5
ns
7tCLCLâ130
80
ns
0
0
ns
tCLCLâ25
tCLCL+25
5
55
ns
tCHCX
18
tCLCX
18
tCLCH
18
tCHCL
18
Shift Register
High time
Low time
Rise time
Fall time
0.38tCLCL
tCLCLâtCLCX
ns
0.38tCLCL
tCLCLâtCHCX
ns
5
ns
5
ns
tXLXL
17
Serial port clock cycle time
12tCLCL
360
ns
tQVXH
17
Output data setup to clock rising edge
10tCLCLâ133
167
ns
tXHQX
17
Output data hold after clock rising edge
2tCLCLâ80
ns
tXHDX
17
Input data hold after clock rising edge
0
0
ns
tXHDV
17
Clock rising edge to input data valid
10tCLCLâ133
167
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
âAC Electrical Characteristicsâ, page 23.
5. Parts are guaranteed to operate down to 0Hz.
2000 Jan 20
24
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